ics8312 Integrated Device Technology, ics8312 Datasheet

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ics8312

Manufacturer Part Number
ics8312
Description
Lvcmos-input Lvcmos-output 1 12 250-mhz Clock Buffer
Manufacturer
Integrated Device Technology
Datasheet

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IDT™ / ICS™ LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER
LOW SKEW, 1-TO-12 LVCMOS /
LVTTL FANOUT BUFFER
G
els. The low impedance LVCMOS outputs are designed to
drive 50Ω series or parallel terminated transmission lines. The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
The ICS8312 is characterized at full 3.3V, 2.5V, and 1.8V,
mixed 3.3V/2.5V, 3.3V/1.8V and 2.5V/1.8V output operating
supply modes. Guaranteed output and part-to-part skew char-
acteristics along with the 1.8V output capabilities makes the
ICS8312 ideal for high performance, single ended applica-
tions that also require a limited output voltage.
8312AY
B
HiPerClockS™
CLK_EN
ICS
ENERAL
LOCK
CLK
OE
The ICS8312 is a low skew, 1-to-12 LVCMOS /
LVTTL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8312 single ended
clock input accepts LVCMOS or LVTTL input lev-
D
IAGRAM
Integrated
Circuit
Systems, Inc.
D
ESCRIPTION
nD
LE
Q
http://www.icst.com/products/hiperclocks.html
12
Q0:Q11
1
1
P
F
• 12 LVCMOS / LVTTL outputs
• LVCMOS / LVTTL clock input
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
• Operating supply modes:
• 0°C to 85°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
Core/Output
3.3V/3.3V,
2.5V/2.5V,
1.8V/1.8V,
3.3V/2.5V,
3.3V/1.8V,
2.5V/1.8V
EATURES
IN
CLK_EN
A
GND
GND
GND
CLK
V
V
LVCMOS / LVTTL F
SSIGNMENT
OE
DD
DD
7mm x 7mm x 1.4mm body package
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
32-Lead LQFP
ICS8312
Y Pacakge
Top View
L
OW
S
ANOUT
KEW
ICS8312
24
23
22
21
20
19
18
17
REV. C JUNE 14, 2004
DATA SHEET
, 1-
Q4
V
Q5
GND
Q6
V
Q7
GND
DDO
DDO
B
TO
UFFER
ICS8312
-12
ICS8312

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