IDT72V8985 Integrated Device Technology, IDT72V8985 Datasheet

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IDT72V8985

Manufacturer Part Number
IDT72V8985
Description
3.3 Volt Time Slot Interchange Digital Switch 256 X 256
Manufacturer
Integrated Device Technology
Datasheet

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 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEATURES:
• • • • •
• • • • •
DESCRIPTION:
a microprocessor. The IDT72V8985 can handle as many as 256, 64 Kbit/s input
and output channels. Those 256 channels are divided into 8 serial inputs and
outputs, each of which consists of 32 channels. The IDT72V8985 provides per-
channel variable or constant throughput delay modes and microprocessor read
NOTE:
1. The RESET Input is only provided on the SSOP package.
FUNCTIONAL BLOCK DIAGRAM
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS
RX0
RX1
RX2
RX3
RX4
RX5
RX6
RX7
The IDT72V8985 is a ST-BUS
256 x 256 channel non-blocking switch
Automatic signal identification (ST-BUS
8 RX inputs—32 channels at 64 Kbit/s per serial line
8 TX outputs—32 channels at 64 Kbit/s per serial line
Three-state serial outputs
Microprocessor Interface (8-bit data bus)
Frame Integrity for data applications
3.3V Power Supply
Available in 44-pin Plastic Leaded Chip Carrier (PLCC),
48-pin Small Shrink Outline Package (SSOP), and 44-pin Plastic
Quad Flatpack (PQFP)
Operating Temperature Range -40° ° ° ° ° C to +85° ° ° ° ° C
3.3V I/O with 5V Tolerant Inputs
Serial Data
Receive
Streams
®
/GCI compatible digital switch controlled by
Memory
Data
3.3 VOLT TIME SLOT INTERCHANGE
DIGITAL SWITCH
256 x 256
®
, GCI)
DS
Microprocessor Interface
C4i
CS
Timing
Control Register
Unit
R/W A0/
F0i
is a trademark of Mitel Corp.
A5
1
V
and write access to individual channels. As an important function of a digital
switch is to maintain sequence integrity and minimize throughput delay, the
IDT72V8985 is an ideal solution for most switching needs.
FUNCTIONAL DESCRIPTION
delay are high priority requirements in today’s integrated data and multimedia
networks. The IDT72V8985 provides these functions on a per-channel basis
using a standard microprocessor control interface. Each of the eight serial lines
is designed to switch 64 Kbit/s PCM or N x 64 Kbit/s data.
slots to control other devices such as ISDN transceivers and trunk interfaces.
Supporting both GCI and ST-BUS
internal circuit to automatically identify the polarity and format of the frame
synchronization.
The serial streams operate continuously at 2.048 Mb/s and are arranged in
125µs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and
eight output (TX0-7) serial streams are provided in the IDT72V8985 device
allowing a complete 256 x 256 channel non-blocking switch matrix to be
constructed. The serial interface clock for the device is 4.096 MHz.
CC
DTA D0/
Frame sequence, constant throughput delay, and guaranteed minimum
In Processor Mode, the microprocessor can access the input and output time
A functional block diagram of the IDT72V8985 device is shown on page 1.
GND
D7
Output MUX
Connection
RESET
Memory
CCO
(1)
®
formats, IDT72V8985 has incorporated an
Serial Data
Transmit
Streams
ODE
AUGUST 2003
IDT72V8985
5707 drw01
DSC-5707/5
TX0
TX1
TX2
TX3
TX4
TX5
TX6
TX7

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IDT72V8985 Summary of contents

Page 1

... Supporting both GCI and ST-BUS internal circuit to automatically identify the polarity and format of the frame synchronization. A functional block diagram of the IDT72V8985 device is shown on page 1. The serial streams operate continuously at 2.048 Mb/s and are arranged in 125µs wide frames each containing 32, 8-bit channels. Eight input (RX0-7) and ...

Page 2

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 PIN CONFIGURATION INDEX RX3 7 RX4 8 RX5 9 RX6 10 RX7 F0i 13 C4i PLCC: 0.05in. pitch, 0.65in. x 0.65in (J44-1, order code: J) TOP VIEW Package Type SSOP: 0.025in. pitch, 0.625in. x 0.295in. ...

Page 3

... This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CCO bit in the Connection Memory HIGH locations. This input (active LOW) puts the IDT72V8985 in its reset state that clears the device internal counters, registers and brings TX0-7 and microport data outputs to a high-impedance state. The time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply ...

Page 4

... DELAY THROUGH THE IDT72V8985 The transfer of information from the input serial streams to the output serial streams results in a delay through the device. The delay through the IDT72V8985 device varies according to the mode selected in the V/C bit of the Connection Memory High. VARIABLE DELAY MODE The delay in Variable Delay Mode is dependent only on the combination of source and destination on the input and output streams ...

Page 5

... Processor Mode; i.e., the contents of the Connection Memory LOW (CML, see Table 5) are output on the output streams once every frame unless the ODE input pin is LOW bit is HIGH, then the IDT72V8985 behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory High (CMH, see Table 4) locations were set to HIGH, regardless of the actual value ...

Page 6

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 Incoming Now Time Slot 28............ Slots For J: DELAY=3 Slots, 32 Slots, 33 Slots, and 34 Slots For G, H, and I: DELAY= 3 slots Incoming Time Slot 28............ Slots For Slot 1 (" ...

Page 7

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 Control Register The Control Register is only accessed when A5=0. All other address bits have no effect when A5=0. When A5 =1, only 32 bytes are randomly accessable via A0-A4 at any one instant. Which 32 bytes are accessed is determined by the state of CRb0 -CRb4. ...

Page 8

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 TABLE 3      CONTROL REGISTER Bit Name 7 SM (Split Memory) When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory, except when the Control Register is accessed again. The Memory Select bits need to specify the memory for the operations. ...

Page 9

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Vcc Symbol Voltage Vi Voltage on Digital Inputs V Voltage on Digital Outputs O I Current at Digital Outputs O T Storage Temperature S P Package Power Dissapation D NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...

Page 10

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 AC ELECTRICAL CHARACTERISTICS  ST-BUS TIMING Symbol Parameter t Frame Pulse Width F0iW t Frame Pulse Setup Time F0iS t Frame Pulse Hold Time F0iH t TX delay Active to Active DAA t RX Setup Time STiS t RX Hold Time ...

Page 11

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Period C4i tCL, tCH Pulse Width t Frame Width High WFH t Frame Setup F0iS t Frame Hold F0iH t Data Delay/Clock Active to Active DAA t RX Input Setup STiS t RX Input Hold ...

Page 12

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 AC ELECTRICAL CHARACTERISTICS  SERIAL STREAM TIMING Symbol Characteristics t TX0-7 Delay - Active to High Z TAZ t TX0-7 Delay - High Z to Active TZA t Output Driver Enable Delay OED t CCO Output Delay XCD t Reset to High Z RSZ t High Z to Reset ...

Page 13

... IDT72V8985 3.3V Time Slot Interchange Digital Switch 256 x 256 AC ELECTRICAL CHARACTERISTICS  MICROPROCESSOR TIMING Symbol Characteristics CS Setup from DS Rising t CSS t R/W Setup from DS Rising RWS t Add Setup from DS Rising ADS CS Hold after DS Falling t CSH t R/W Hold after DS Falling RWH t Add Hold after DS Falling ADH ...

Page 14

ORDERING INFORMATION IDT XXXXXX XX Device Type Package DATASHEET DOCUMENT HISTORY 05/24/2000 pgs and 14. 08/21/2000 pgs and 14. 01/24/2001 pgs. 1 and 9. 04/05/2001 pg. 11. 03/10/2003 pg. 13. 05/09/2003 pgs and ...

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