lmk02002 National Semiconductor Corporation, lmk02002 Datasheet

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lmk02002

Manufacturer Part Number
lmk02002
Description
Precision Clock Conditioner With Integrated Pll
Manufacturer
National Semiconductor Corporation
Datasheet
© 2007 National Semiconductor Corporation
LMK02002
Precision Clock Conditioner with Integrated PLL
General Description
The LMK02002 precision clock conditioner combines the
functions of jitter cleaning/reconditioning, multiplication, and
distribution of a reference clock. The device integrates a high
performance Integer-N Phase Locked Loop (PLL), and four
LVPECL clock output distribution blocks.
Each clock distribution block includes a programmable di-
vider, a phase synchronization circuit, a programmable delay,
a clock output mux, and an LVPECL output buffer. This allows
multiple integer-related and phase-adjusted copies of the ref-
erence to be distributed to eight system components.
The clock conditioner comes in a 48-pin LLP package and is
footprint compatible with other clocking devices in the same
family.
Functional Block Diagram
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
300233
Features
Target Applications
20 fs additive jitter
Integrated Integer-N PLL with outstanding normalized
phase noise contribution of -224 dBc/Hz
Clock output frequency range of 1 to 800 MHz
4 LVPECL clock outputs
Dedicated divider and delay blocks on each clock output
Pin compatible family of clocking devices
3.15 to 3.45 V operation
Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
Data Converter Clocking
Networking, SONET/SDH, DSLAM
Wireless Infrastructure
Medical
Test and Measurement
Military / Aerospace
PRELIMINARY
www.national.com
August 2007
30023301

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lmk02002 Summary of contents

Page 1

... LMK02002 Precision Clock Conditioner with Integrated PLL General Description The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks. ...

Page 2

Connection Diagram Pin Descriptions Pin # 14, 15, 17, 18, 20, 21, 23 13, 16, 19, 22, 26, Vcc1, Vcc2, Vcc3, Vcc4, Vcc5, Vcc6, Vcc7, 30, 31, 33, 37, 40, 43, 46 Vcc8, ...

Page 3

Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Parameter Power Supply Voltage Input Voltage Storage Temperature Range Lead Temperature (solder 4 s) Junction Temperature Recommended Operating Conditions ...

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Symbol Parameter f Phase Detector Frequency COMP I CPout Charge Pump Source Current SRCE I CPout Charge Pump Sink Current SINK I TRI Charge Pump TRI-STATE CPout Magnitude of Charge Pump I %MIS CPout Sink vs. Source Current Mismatch Magnitude ...

Page 5

Symbol Parameter V High-Level Input Voltage IH V Low-Level Input Voltage IL I High-Level Input Current IH I Low-Level Input Current IL t Data to Clock Set Up Time CS t Data to Clock Hold Time CH t Clock Pulse ...

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Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current Charge Pump Sink Current Charge Pump Sink Current Charge Pump Source Current Charge ...

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... Functional Description The LMK02002 precision clock conditioner combines the functions of jitter cleaning/reconditioning, multiplication, and distribution of a reference clock. The device integrates a high performance Integer-N Phase Locked Loop (PLL), and four LVPECL clock output distribution blocks. Each clock distribution block includes a programmable di- vider, a phase synchronization circuit, a programmable delay, a clock output mux, and an LVPECL output buffer ...

Page 8

... General Programming Information The LMK02002 device is programmed using several 32-bit registers which control the device's operation. The registers consist of a data field and an address field. The last 4 register bits, ADDR[3:0] form the address field. The remaining 28 bits form the data field DATA[27:0]. ...

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CLKout0_EN CLKout1_EN CLKout2_EN CLKout3_EN RESET Register DIV4 PLL_CP_POL TRI-STATE POWERDOWN EN_CLKout_Global 9 www.national.com ...

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REGISTER Registers R4 through R7 control the eight clock outputs. Reg- ister R4 controls CLKout0, Register R5 controls CLKout1, and so on. There is one additional bit in register R0 called RESET. Aside from this, the ...

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... Not divided; Phase detector frequency ≤ 20 MHz (default) 1 Divided by 4; Phase detector frequency > 20 MHz 2.5 REGISTER R14 The LMK02002 requires register R14 to be programmed as shown in the register map (see 2.2). 2.5.1 PLL_R[11: Divider Value These bits program the PLL R Divider and are programmed in binary fashion. PLL_R[11:0] 0 ...

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Register R15 2.6.1 PLL_N[17:0] -- PLL N Divider These bits program the divide value for the PLL N Divider. The PLL N Divider follows the VCO Divider and precedes the PLL phase detector. Since the VCO Divider is also ...

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... Application Information 3.1 SYSTEM LEVEL DIAGRAM The following shows the LMK02002 in a typical application. In this setup the clock may be multiplied, reconditioned, and redistributed. 3.2 BIAS PIN To properly use the device, bypass Bias (pin 36) with a low leakage 1 µF capacitor connected to Vcc. This is important for low noise performance. ...

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... When an LVPECL output is disabled, the emitter resistor voltage is ~1.07 V. Therefore the power dissipated in each emitter resistor is approximately (1.07 V) 3.5 THERMAL MANAGEMENT Power consumption of the LMK02002 can be high enough to require attention to thermal management. For reliability and performance reasons the die temperature should be limited to a maximum of 125 °C. That is estimate, T temperature) plus device power consumption times θ ...

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To minimize junction temperature it is recommended that a simple heat sink be built into the PCB (if the ground plane layer is not exposed). This is done by including a copper area of about 2 square inches on the ...

Page 16

... Physical Dimensions Order Number LMK02002ISQ LMK02002ISQX www.national.com inches (millimeters) unless otherwise noted Leadless Leadframe Package (Bottom View) 48 Pin LLP (SQA48A) Package Package Marking K02002 I 250 Unit Tape and Reel K02002 I 2500 Unit Tape and Reel 16 Packing LVPECL Outputs 4 4 ...

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Notes 17 www.national.com ...

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... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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