LMX2487E National Semiconductor Corporation, LMX2487E Datasheet

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LMX2487E

Manufacturer Part Number
LMX2487E
Description
7.5 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 3.0 Ghz Integer Pll
Manufacturer
National Semiconductor Corporation
Datasheet

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© 2007 National Semiconductor Corporation
LMX2487E
7.5 GHz High Performance Delta-Sigma Low Power Dual
PLLatinum ™ Frequency Synthesizers with 3.0 GHz Integer
PLL
General Description
The LMX2487E is a low power, high performance delta-sigma
fractional-N PLL with an auxiliary integer-N PLL. It is fabricat-
ed using National Semiconductor’s advanced process.
With delta-sigma architecture, fractional spurs at lower offset
frequencies are pushed to higher frequencies outside the loop
bandwidth. The ability to push close in spur and phase noise
energy to higher frequencies is a direct function of the mod-
ulator order. Unlike analog compensation, the digital feed-
back technique used in the LMX2487E is highly resistant to
changes in temperature and variations in wafer processing.
The LMX2487E delta-sigma modulator is programmable up
to fourth order, which allows the designer to select the opti-
mum modulator order to fit the phase noise, spur, and lock
time requirements of the system.
Serial data for programming the LMX2487E is transferred via
a three line high speed (20 MHz) MICROWIRE interface. The
LMX2487E offers fine frequency resolution, low spurs, fast
programming speed, and a single word write to change the
frequency. This makes it ideal for direct digital modulation
applications, where the N counter is directly modulated with
information. The LMX2487E is available in a 24 lead
4.0 X 4.0 X 0.8 mm LLP package.
Applications
Functional Block Diagram
PLLatinum ™ is a trademark of National Semiconductor Corporation.
Cellular phones and base stations
Direct digital modulation applications
Satellite and cable TV tuners
300139
Features
Quadruple Modulus Prescalers for Lower Divide Ratios
Advanced Delta Sigma Fractional Compensation
Features for Improved Lock Times and Programming
Wide Operating Range
Useful Features
WLAN Standards
RF PLL: 16/17/20/21 or 32/33/36/37
IF PLL: 8/9 or 16/17
12 bit or 22 bit selectable fractional modulus
Up to 4th order programmable delta-sigma modulator
Fastlock / Cycle slip reduction
Integrated time-out counter
Single word write to change frequencies with Fastlock
LMX2487E RF PLL: 3.0 GHz to 7.5 GHz
Digital lock detect output
Hardware and software power-down control
On-chip crystal reference frequency doubler.
RF phase comparison frequency up to 50 MHz
2.5 to 3.6 volt operation with I
CC
30013901
= 8.5 mA at 3.0 V
www.national.com
May 2007

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LMX2487E Summary of contents

Page 1

... The ability to push close in spur and phase noise energy to higher frequencies is a direct function of the mod- ulator order. Unlike analog compensation, the digital feed- back technique used in the LMX2487E is highly resistant to changes in temperature and variations in wafer processing. The LMX2487E delta-sigma modulator is programmable up ...

Page 2

Connection Diagram Pin Descriptions Pin # Pin Name I/O 0 GND - 1 CPoutRF O 2 GND - 3 VddRF1 - 4 FinRF I 5 FinRF DATA I 8 CLK I 9 VddRF2 - 10 ...

Page 3

Absolute Maximum Ratings Parameter Power Supply Voltage Voltage on any pin with GND = 0V Storage Temperature Range Lead Temperature (Solder 4 sec.) Recommended Operating Conditions Parameter Power Supply Voltage (Note 1) Operating Temperature Note 1: “Absolute Maximum Ratings” indicate ...

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Symbol Parameter RF Charge Pump Sink I SINK Current CPoutRF (Note 4) RF Charge Pump TRI- I TRI STATE Current CPoutRF Magnitude Magnitude Sink | I %MIS | CPoutRF vs. CP Source Mismatch Magnitude ...

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Symbol Parameter PHASE NOISE RF Synthesizer L RF Normalized Phase Noise F1Hz Contribution(Note 6) IF Synthesizer L IF Normalized Phase Noise F1Hz Contribution DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF) V High-Level Input Voltage IH V Low-Level Input ...

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Typical Performance Characteristics : Sensitivity www.national.com (Note 7) RF PLL Fin Sensitivity T = 25°C, RF_P = PLL Fin Sensitivity V = 3.0 V, RF_P = 30013945 30013946 ...

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IF PLL Fin Sensitivity T = 25°C, IF_P = PLL Fin Sensitivity V = 3.0 V, IF_P = 30013947 30013948 www.national.com ...

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OSCin Sensitivity T = 25°C, OSC_2X = 0 A OSCin Sensitivity V = 3.0 V, OSC_2X = 30013949 30013956 ...

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OSCin Sensitivity T = 25°C, OSC_2X =1 A OSCin Sensitivity V = 3.0 V, OSC_2X = 30013973 30013974 www.national.com ...

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Typical Performance Characteristic : FinRF Input Impedance Frequency (MHz) 3000 3200 3400 3600 3800 4000 4250 4500 4750 5000 5250 5500 5750 6000 6250 6500 6750 7000 7250 7500 7750 8000 8250 www.national.com FinRF Input Impedance Real (Ohms ...

Page 11

Typical Performance Characteristic : FinIF Input Impedance Frequency (MHz) 100 150 200 250 300 400 500 600 700 800 900 1000 1200 1400 1600 1800 2000 2200 2300 2400 2600 2800 3000 FinIF Input Impedance Real (Ohms) 508 456 420 ...

Page 12

Typical Performance Characteristic : OSCin Input Impedance Frequency (MHz) Real 5 1730 10 846 20 466 30 351 40 316 50 278 60 261 70 252 80 239 90 234 100 230 110 225 120 219 130 214 140 208 ...

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Typical Performance Characteristics : Currents (Note 7) Power Supply Current CE = High RF PLL Charge Pump Current V = 3.0 Volts CC 13 30013959 30013967 www.national.com ...

Page 14

IF PLL Charge Pump Current V = 3.0 Volts CC Charge Pump Leakage RF PLL V = 3.0 Volts CC 14 30013965 30013964 ...

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Note 7: Typical performance characteristics do not imply any sort of guarantee. Guaranteed specifications are in the electrical characteristics section. Charge Pump Leakage IF PLL V = 3.0 Volts CC 15 30013963 www.national.com ...

Page 16

Bench Test Setups Charge Pump Current Measurement Procedure The above block diagram shows the test procedure for testing the RF and IF charge pumps. These tests include absolute current level, mismatch, and leakage measurement. In order to measure the charge ...

Page 17

Charge Pump Current Specification Definitions I1 = Charge Pump Sink Current at V CPout I2 = Charge Pump Sink Current at V CPout I3 = Charge Pump Sink Current at V CPout I4 = Charge Pump Source Current at V ...

Page 18

... The expected frequency at the Ftest/LD pin should be the signal generator frequency divided by twice the corresponding counter value. The factor of two comes in because the LMX2487E has a flip-flop which divides this frequency by two to make the duty cycle 50% in order to make it easier to read with the frequency counter. The frequency counter input impedance should be set to high impedance ...

Page 19

... Input Impedance Measurement Procedure The above block diagram shows the test setup used for measuring the input impedance for the LMX2487E. The DC blocking capacitor used between the input SMA connector and the pin being measured must be changed to a zero Ohm resistor. This procedure applies to the FinRF, FinIF, and OSCin pins ...

Page 20

... The small capacitor should be placed as close as possible to the pin. The power down state of the LMX2487E is controlled by many factors. The one factor that overrides all other factors is the CE pin. If this pin is low, the part will be powered down. As- ...

Page 21

CE Pin RF_PD ATPU Bit Enabled + Write Counter Low X X High X Yes High 0 No High 1 No 1.7 DIGITAL LOCK DETECT OPERATION The RF PLL digital lock detect circuitry compares the differ- ence ...

Page 22

... CYCLE SLIP REDUCTION AND FASTLOCK The LMX2487E offers both cycle slip reduction (CSR) and Fastlock with timeout counter support. This means that it re- quires no additional programming overhead to use them generally recommended that the charge pump current in the steady state less in order to use cycle slip reduction, and 4X or less in steady state in order to use Fastlock ...

Page 23

... To get a more accurate estimate requires more simula- tion tools, or trial and error. 1.8.3 Capacitor Dielectric Considerations for Lock Time The LMX2487E has a high fractional modulus and high charge pump gain for the lowest possible phase noise. One consideration is that the reduced N value and higher charge pump may cause the capacitors in the loop filter to become larger in value ...

Page 24

... Control Register Content Map Because the LMX2487E registers are complicated, they are organized into two groups, basic and advanced. The first four registers are basic registers that contain critical information necessary for the PLL to achieve lock. The last 5 registers are for features that optimize spur, phase noise, and lock time performance ...

Page 25

... Quick Start Register Map Although it is highly recommended that the user eventually take advantage of all the modes of the LMX2487E, the quick start register map is shown in order for the user to get the part up and running quickly using only those bits critical for basic functionality. The following default conditions for this programming state are a third order delta-sigma modulator in 12-bit mode with no dithering and no Fastlock ...

Page 26

R0 REGISTER Note that this register has only one control bit, so the N counter value to be changed with a single write statement to the PLL. REGISTER 2.1.1 RF_FN[11:0] -- Fractional Numerator for ...

Page 27

R1 REGISTER REGISTER RF_PD RF_P 2.2.1 RF_FD[11: PLL Fractional Denominator The function of these bits are ...

Page 28

R2 REGISTER REGISTER IF_PD 2.3.1 IF_N[18: Divider Value IF_N Counter Programming with the 8/9 Prescaler (IF_P=0) N Value ≤ values less than or equal to 23 are prohibited because IF_B ...

Page 29

R3 REGISTER REGISTER ACCESS[3:0] 2.4.1 IF_R[11: Divider Value For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for ...

Page 30

Register This corresponds to the following bit ...

Page 31

R4 REGISTER This register controls the conditions for the RF PLL in Fastlock. REGISTER ATPU 2.5.1 MUX[3:0] Frequency Out & Lock Detect MUX ...

Page 32

OSC_OUT Oscillator Output Buffer Enable OSC_OUT 0 1 2.5.6 OSC2X -- Oscillator Doubler Enable When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF R counters ...

Page 33

R5 REGISTER REGISTER RF_FD[21:12] 2.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[ the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12] ...

Page 34

R6 REGISTER REGISTER CSR[1:0] RF_CPF[3:0] 2.7.1 RF_TOC -- RF Time Out Counter and Control for FLoutRF Pin The RF_TOC[13:0] word controls the operation of the RF Fastlock circuitry as well as the function of ...

Page 35

CSR CSR State Sample Rate Reduction Factor Disabled Enabled Enabled Enabled 35 1 1/2 1/4 1/16 www.national.com ...

Page 36

R7 REGISTER REGISTER 2.8.1 DIV4 -- RF Digital Lock Detect Divide By 4 Because the digital lock detect function ...

Page 37

... Physical Dimensions inches (millimeters) unless otherwise noted Order Number LMX2487ESQXfor 4500 Unit Reel Plastic Quad LLP (SQ), Bottom View Order Number LMX2487ESQ for 1000 Unit Reel NS Package Number SQA24A 37 www.national.com ...

Page 38

... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...

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