LTC1325 LINER [Linear Technology], LTC1325 Datasheet
LTC1325
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LTC1325 Summary of contents
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... DD LTC1325 for fault conditions. The charge mode is termi- nated by the P while monitoring any combination of battery voltage and temperature, ambient temperature and charge time. The LTC1325 also monitors the battery for fault conditions before and during charging ...
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... CLK CS DIN CLK CS DIN U W INFORMATION ORDER PART TOP VIEW NUMBER PGATE LTC1325CN 16 DIS LTC1325CSW 15 V BAT 14 T BAT 13 T AMB SENSE 10 FILTER SW PACKAGE 18-LEAD PLASTIC SO WIDE = ( 100 C/ W (SW) JA MIN TYP MAX 4 ...
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... Note 4: Linearity error is specified between the actual end points of the A/D transfer curve. Note 5: Channel leakage is measured after channel selection. Note 6: Gas gauge offset excludes A/D offset error. Note (Duty Ratio)/R DAC voltage with control bits VR1 = VR0 = 1, duty ratio = 1 and R determined by the user. LTC1325 MIN TYP MAX UNITS 0.4 V 2.4 V ...
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... LTC1325 W U TYPICAL PERFORMANCE CHARACTERISTICS Regulator Output Voltage vs Load Current 3.077 3.076 V = 16V DD 3.075 V = 12V DD 3.074 V = 4.5V DD 3.073 3.072 3.071 3.070 0.5 1.0 1.5 2.0 2.5 3.5 0 3.0 LOAD CURRENT (mA) 1325 G01 Charge Current vs Battery Voltage 160 VR1 = 1, VR0 = 1 140 V = 12V 120 DD SENSE L = 100 H, P1: IRF9531 ...
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... TEMPERATURE ( C) LTC1325 Differential Nonlinearity 1 12V 500kHz CLK 0.5 0 –0.5 –1 128 384 512 640 256 CODE LTC1325 G11 Integral Nonlinearity 1 12V 500kHz CLK 0.5 0 –0.5 –1 128 256 384 512 640 CODE 1325 G14 CLK to D Valid Delay Time ...
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... LTC1325 PIN FUNCTIONS REG (Pin 1): Internal Regulator Output. The regulator provides a steady 3.072V to the internal analog circuitry and provides a temperature stable reference voltage for generating MCV, HTF, LTF and thermistor bias voltages with external resistors. Requires a 4 greater bypass capacitor to ground. ...
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... ANALOG AND DIGITAL ADC REFERENCE DIS t OUT 6 LTF 8 HTF 7 MCV AMB 14 T BAT 15 V BAT 4 CHARGE 11 SENSE 10 FILTER 17 PGATE LTC1325 • BD Load Circuit for t and t dis en TEST POINT 5V t WAVEFORM 2, t dis 3k D OUT t WAVEFORM 1 dis 100pF LTC1325 • TC02 en 7 ...
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... SUCH THAT THE OUTPUT IS LOW UNLESS DISABLED BY CS. Voltage Waveforms for t en VR1 THREE-STATE Rise and Fall Times OUT r f 2.4V 0. LTC1325 • TC04 Voltage Waveforms for t dis 2V 90% t dis 10% LTC1325 • TC06 0. NULL D9 0.4V LTC1325 • TC07 ...
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... ADC measurement is made and the 10-bit reading and chip status word are shifted out. The command word configures the LTC1325 and forces it into one of five modes: power shutdown, idle, discharge, charge or gas gauge mode. ...
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... DR1 DR2 Bits ADC Data Input Select (DS0 to DS2) DS2, DS1 and DS0 select which circuit is connected to the 22 ADC input. Do not use unlisted combinations. LTC1325 • F01 DS2 DS1 input after Bits 9 to 12: Battery Divider Ratio Select (DIV0 to DIV3) DIV3, DIV2, DIV1 and DIV0 select the division ratio for the voltage divider across the battery ...
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... DAC 160 FMCV FEDV FHTF FLTF t FS OUT LTC1325 • F02 Figure 2. Status Word pin falls below BAT (see Figure 3). TRK – 1.8) < V < BAT DD < (V – 1. below CELL > 100mV < 100mV 11 CHRG . The ...
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... CONDITIONS 0 No Fail-Safe Has Occurred 1 Fail-Safe Has Occurred DETAILED DESCRIPTION Fault Conditions The LTC1325 monitors the battery for fault conditions before and during discharge and charge (see Figure 3). They include: battery removed/present (BATP), battery reversed/shorted (BATR), maximum cell voltage exceeded V 1.8V C1 ...
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... The rising edge of the oscillator waveform triggers the one shot which sets the flip-flop output high. This turns on the external PFET P1 by pulling its gate low via the FET driver. With P1 on, the current through the inductor L1 starts LTC1325 by the internal driver BATP = 1, BATR = 0, FMCV = 0, FEDV = X, ...
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... Sense pin or if the gas gauge used, selecting R SENSE V DD 4.5V TO 16V PGATE P1 R TRK IRF9Z30 DIS D1 1N5818 L1 R DIS BATTERY N1 IRFZ34 SENSE SENSE FILTER CHIP BOUNDARY LTC1325 • F04 SENSE so that R /I < 140mV. SENSE CHRG ...
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... Data transfer is initiated by a falling chip select CS signal OUT After CS falls, the LTC1325 looks for a start bit on D start bit is the first “logical one” clocked into the D after CS goes low. The LTC1325 will ignore all leading zeros which precede this logical one. After the start bit is received, the 21 other control bits are shifted into the D pin to configure the LTC1325 and start a conversion ...
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... The processor pin connected to this data line should be configurable as either an input or an output. The LTC1325 will take control of the data line and drive it low after the 23rd falling CLK edge after the start bit is received. Therefore the processor port must be switched to an input before this happens to avoid a conflict ...
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... LTC1325 • F05 HARDWARE DESIGN PROCEDURE This section discusses the considerations in selecting each component of a simple battery charger (see Figures 3 and 4). Further applications assistance is provided BAT AMB Application Note 64, using the LTC1325 Battery Manage- ( DIV ment IC SENSE [see equation a. LTC1325 ...
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... V Supply: V should be at least 1.8V above the DD DD maximum battery voltage to prevent a BATP = 0 error when the LTC1325 is in charge or discharge mode. If this requirement cannot be met in a specific applica- tion, an external battery divider should be connected between the V ...
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... To prolong battery life, manufacturers generally recommend discharge temperatures that are similar to the charge limits. For this reason, the LTC1325 recognizes the same LTF and HTF limits in both charge and discharge modes. MCV should be set just above the charging voltage per cell given in battery specifications ...
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... DD The Wide Voltage Battery Charger circuit in the Typical Application section shows low cost implementations of all three sub-circuits. C1, R11 and D4 generate a 15V V the LTC1325. D3, R12 and C2 form a level shifter. The zener D3 is chosen to clamp the source gate voltage of the 20 U PFET to within the maximum gate source voltage rating of the latter ...
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... BAT CELL 5. The PS bit should always that the LTC1325 does not go into shutdown mode. 6. The DR0 to DR2 should not select any of the test modes. It may assume different settings between Fast charge and Top Off charge in order to alter the charging current. ...
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... Peripheral Control Register (SPCR) to select master mode, set baud rate and clock timing relationship. Another byte is written to the Port D Direction Register (DDRD) to set MOSI, SCK and bit 0 (CS of LTC1325) as outputs. The 68HC11 clocks in data from the LTC1325 simultaneously under the control of SCK. The microprocessor transmits the LTC1325 command word in 4 bytes ...
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... BAT OMIT WHEN V < 16V. DC NOTE 5: EXTERNAL BATTERY DIVIDER. NEEDED WHEN MAXIMUM BATTERY VOLTAGE, V > 16V. BAT NOTE UNCOMMITTED A/D CHANNEL. IN LTC1325 COMMENTS $1029 Check for SPI transfer LOOP4 complete bit $102A Get A/D high byte #$03 Mask off unwanted bits HIDATA ...
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... LTC1325 PACKAGE DESCRIPTION 0.300 – 0.325 0.130 0.005 (7.620 – 8.255) (3.302 0.127) 0.015 (0.381) MIN 0.009 – 0.015 (0.229 – 0.381) +0.025 0.325 –0.015 0.125 +0.635 (3.175) 8.255 –0.381 MIN *THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm) 0.291 – ...