LTC1753 LINER [Linear Technology], LTC1753 Datasheet
LTC1753
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LTC1753 Summary of contents
Page 1
... N- channel FET, providing an adjustable current limit without an external low value sense resistor. The LTC1753 free-runs at 300kHz and can be synchronized to a faster external clock if desired. It provides a phase lead compensation scheme and under harsh loading conditions, ® ...
Page 2
... 12V, OUTEN = 0, VID0 to VID4 Floating CC (Figure 4) (Note 11) (Note 11 TOP VIEW ORDER PART NUMBER OUTEN 18 VID0 LTC1753CG 17 VID1 LTC1753CSW 16 VID2 15 VID3 14 VID4 13 PWRGD 12 FAULT PACKAGE 20-LEAD PLASTIC SO = 100 100 C/ W (SW MIN ...
Page 3
... A(I SSIL current ratio is designed to be 5:1. Note 10: When VID0 to VID4 are all HIGH, the LTC1753 will be forced to shut down internally. The OUTEN trip voltages are guaranteed by design for all other input codes. Note 11: This parameter is guaranteed by design and correlation and is not tested in production ...
Page 4
... LTC1753 W U TYPICAL PERFOR A CE CHARACTERISTICS Typical 1.3V V Distribution OUT 50 TOTAL SAMPLE SIZE = 500 100 1.275 1.285 1.295 1.305 1.315 OUTPUT VOLTAGE (V) 1753 G01 Load Regulation 2.825 REFER TO TYPICAL APPLICATION 2.820 CIRCUIT FIGURE 5V 12V ...
Page 5
... TEMPERATURE ( C) = 2.8V V OUT 50mV/DIV 10 I LOAD 5A/DIV 1753 G16 LTC1753 Soft-Start Source Current vs Temperature – 8 – 9 –10 –11 –12 –13 –14 –15 –16 125 – 50 – TEMPERATURE ( C) 1753 G11 PV Supply Current CC vs Gate Capacitance ...
Page 6
... In hard current limit, the soft-start capacitor will be forced low immedi- ately and the LTC1753 will rerun a complete soft-start cycle current through Q1 will not exceed the current limit value. ...
Page 7
... Figure 11. When the OUTEN input voltage drops below 1.7V, the drivers are internally disabled to prevent the MOSFETs from heating further. If OUTEN is less than 1.2V for longer than 30 s, the LTC1753 will enter shutdown mode. The internal oscillator can be synchronized to a faster external clock by applying the external clocking signal to the OUTEN pin ...
Page 8
... LTC1753 W BLOCK DIAGRA + 113% V REF FC – OUTEN 19 COMP REF MHCL HCL MONO 8 12 FAULT DISDR LOGIC SYSTEM POWER DOWN – R PWM S + ERR MIN – – + – V – REF REF – MAX I MAX + LVC – ...
Page 9
... COMP SGND GND SENSE NC Figure 12V + 0 RISE/FALL 5000pF LTC1753 G2 G2 RISE/FALL 5000pF SGND GND Figure 4 LTC1753 1200 F 4 Q1A* FB † Q1* G1 1.3 H 15A NC + †† C OUT 2700 F Q2A Q2 ...
Page 10
... MOSFETs or the microprocessor. Two thresh- old levels are provided internally. When OUTEN drops to 1.7V, the G1 and G2 pins will be forced low. If OUTEN is pulled below 1.2V, the LTC1753 will go into shutdown mode, cutting the supply current to a minimum. If thermal shutdown is not required, OUTEN can be connected to a ...
Page 11
... During start-up, the COMP pin is clamped to a diode drop above the voltage at the SS pin. This prevents the error amplifier, ERR, from forcing the loop to 100% duty cycle. The LTC1753 will begin to operate at low duty cycle as the SS pin rises above about 1. continues to rise, Q and C amplifier begins to regulate the output ...
Page 12
... A low level at OUTEN stops all internal switching, pulls COMP and SS to ground internally and turns Q1 and Q2 off. PWRGD is pulled low, and FAULT is left floating. In shutdown, the LTC1753 quiescent current drops to about 130 A. The residual current is used to keep the thermistor sensing circuit at OUTEN alive ...
Page 13
... If the external frequency is much higher than the natural free-running frequency, the peak-to-peak sawtooth amplitude within the LTC1753 will decrease. Since the loop gain is inversely proportional to the amplitude of the sawtooth, the com- pensation network may need to be adjusted slightly. Note that the temperature sensing circuitry does not operate when external synchronization is used ...
Page 14
... Siliconix Si4410DY or International Rectifier IRF7413 (both in SO-8) or Siliconix SUD50N03 or Motorola MTD20N03HDL (both in D PAK) are small footprint sur- face mount devices with R of gate drive that work well in LTC1753 circuits. With value of: higher output voltages, the R MAX significantly lower than that for Q2. These conditions can often be met by paralleling two MOSFETs for Q1 and using a single device for Q2 ...
Page 15
... To minimize this effect, the inductor value should usually be in the range for most typical 5V input LTC1753 circuits. To optimize performance, different combinations of input and output voltages and expected loads may require different inductor values ...
Page 16
... Refer to the Feedback Loop Compensation section for details. Feedback Loop Compensation The LTC1753 voltage feedback loop is compensated at the COMP pin, attached to the output node of the internal g error amplifier. The feedback loop can generally be com- pensated properly with network from COMP to GND as shown in Figure 7a ...
Page 17
... LC ESR f CO Figure 7b. Bode Plot of the LTC1753 Overall Transfer Function W U poor load transient response despite the improvement in output voltage ripple. To resolve this problem, a small capacitor can be con- nected between the SENSE and V zero pair in the loop compensation. The zero location is ...
Page 18
... LTC1753 U U APPLICATIO S I FOR ATIO response using a network analyzer to find the actual loop poles and zeros. Table 5 shows the suggested compensation components for 5V input applications based on the inductor and output capacitor values. The values were calculated using mul- tiple paralleled 330 F AVX TPS series surface mount tantalum capacitors as the output capacitor ...
Page 19
... Once PWRGD goes low, the internal circuitry watches for the output voltage to exceed 113% of the rated voltage. If this happens, FAULT will be triggered. Once FAULT is triggered, G1 and G2 will be forced low immediately and the LTC1753 will remain in this state until V supply is recycled or OUTEN is toggled. 13% 3% ...
Page 20
... Care should be taken to isolate SENSE and V inductor switching signal required between the SENSE pin and the SGND pin next to the LTC1753. If PWRGD or FAULT are in the wrong logic state for nonobvious reasons, check the layout of the SENSE and V traces carefully ...
Page 21
... BOLD LINES INDICATE HIGH CURRENT PATHS = GROUND PLANE 0 0 IMAX R IFB Figure 10. LTC1753 Layout Diagram LTC1753 1 20 LTC1753 OUTEN VID0 VID0 3 GND 17 VID1 VID1 4 SGND 5.6k 16 VID2 VID2 5 5. ...
Page 22
... LTC1753 PACKAGE DESCRIPTIO 5.20 – 5.38** (0.205 – 0.212) 0.13 – 0.22 0.55 – 0.95 (0.005 – 0.009) (0.022 – 0.037) NOTE: DIMENSIONS ARE IN MILLIMETERS * DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.152mm (0.006") PER SIDE ** DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.254mm (0.010") PER SIDE ...
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... DWG # 05-08-1620 NOTE 0.093 – 0.104 45 (2.362 – 2.642) 0 – 8 TYP 0.050 (1.270) BSC 0.014 – 0.019 (0.356 – 0.482) TYP LTC1753 0.496 – 0.512* (12.598 – 13.005 0.394 – 0.419 (10.007 – 10.643 0.037 – ...
Page 24
... C1 DALE 150pF NTHS-1206N02 MOUNT THERMISTER IN CLOSE THERMAL PROXIMITY TO Q1 Figure 11. Single Supply LTC1753 5V to 1.3V-3.5V Application with Thermal Monitor RELATED PARTS PART NUMBER DESCRIPTION LTC1530 High Power Synchronous Step-Down Controller LTC1628 Dual High Efficiency Low Noise Synchronous Step-Down Switching Regulator LTC1553L ...