LTC2207 LINER [Linear Technology], LTC2207 Datasheet

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LTC2207

Manufacturer Part Number
LTC2207
Description
16-Bit, 105Msps/80Msps ADCs
Manufacturer
LINER [Linear Technology]
Datasheet

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Part Number:
LTC2207CUK#PBF
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LTC2207CUK#PBF
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LTC2207CUK-14#PBF
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FEATURES
APPLICATIO S
TYPICAL APPLICATIO
ANALOG
INPUT
Sample Rate: 105Msps/80Msps
78.2dBFS Noise Floor
100dB SFDR
SFDR >82dB at 250MHz (1.5V
PGA Front End (2.25V
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
Power Dissipation: 900mW/725mW
Optional Clock Duty Cycle Stabilizer
Out-of-Range Indicator
Pin Compatible Family
48-Pin 7mm × 7mm QFN Package
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
V
2.2µF
AIN
AIN
CM
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
40Msps: LTC2204 (16-Bit)
25Msps: LTC2203 (16-Bit) Single-Ended Clock
10Msps: LTC2202 (16-Bit) Single-Ended Clock
+
COMMON MODE
BIAS VOLTAGE
+
CLOCK/DUTY
ENC
CONTROL
AMP
S/H
CYCLE
1.25V
+
ENC
U
INTERNAL ADC
GENERATOR
REFERENCE
PIPELINED
ADC CORE
16-BIT
P-P
3.3V
SENSE
PGA
or 1.5V
SHDN
ADC CONTROL INPUTS
P-P
U
SHIFT REGISTER
CORRECTION
LOGIC AND
DITH
P-P
Input Range)
MODE
Input Range)
OE
DRIVERS
OUTPUT
RAND
OV
OGND
GND
V
DD
DD
OF
CLKOUT
CLKOUT
D15
D0
0.1µF
0.1µF
DESCRIPTIO
The LTC
16-bit A/D converters designed for digitizing high fre-
quency, wide dynamic range signals up to input frequencies
of 700MHz. The input range of the ADC can be optimized
with the PGA front end.
The LTC2207/LTC2206 are perfect for demanding commu-
nications applications, with AC performance that includes
78.2dB Noise Floor and 100dB spurious free dynamic range
(SFDR). Ultralow jitter of 80fs
high input frequencies with excellent noise performance.
Maximum DC specs include ±4LSB INL, ±1LSB DNL (no
missing codes) over temperature.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
All other trademarks are the property of their respective owners. Patents Pending.
0.5V TO 3.6V
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
+
0.1µF
16-Bit, 105Msps/80Msps
®
+
2207/LTC2206 are 105Msps/80Msps, sampling
and ENC
22054 TA01
0.1µF
3.3V
U
LTC2207/LTC2206
inputs may be driven differentially
–100
–110
–120
–130
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
0
LTC2207: 64K Point FFT,
f
RMS
IN
PGA = 0, 105Msps
= 14.8MHz, –1dBFS,
10
allows undersampling of
FREQUENCY (MHz)
20
30
ADCs
40
22076 G05
50
22076fa
1

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LTC2207 Summary of contents

Page 1

... The input range of the ADC can be optimized Input Range) with the PGA front end. P-P The LTC2207/LTC2206 are perfect for demanding commu- nications applications, with AC performance that includes 78.2dB Noise Floor and 100dB spurious free dynamic range (SFDR). Ultralow jitter of 80fs high input frequencies with excellent noise performance. Maximum DC specs include ± ...

Page 2

... Digital Input Voltage .....................–0. Digital Output Voltage ................ –0.3V to (OV Power Dissipation ............................................ 2000mW Operating Temperature Range LTC2207C/LTC2206C ............................... 0°C to 70°C LTC2207I/LTC2206I ............................. –40°C to 85°C Storage Temperature Range .................. –65°C to 150°C Digital Output Supply Voltage (OV DD CONVERTER CHARACTERISTICS temperature range, otherwise specifi cations are at T ...

Page 3

... IN MIN 76.5 ● 76.2 73.8 ● 73.4 87 ● ● 83 LTC2207/LTC2206 MIN TYP MAX ● 1.5 to 2.25 ● 1 1.25 1.5 ● –1 1 ● – 6.7 1 700 LTC2206 LTC2207 TYP MAX MIN TYP MAX 77.9 77.9 75.5 75.5 77.8 76.5 77.8 77.5 76.2 77.5 75.4 75.4 77.5 77.5 75.3 75.3 76.7 76.7 74.8 73.8 74.8 74.5 73.4 74.5 76.2 76.2 75.4 75.4 100 100 100 100 ...

Page 4

... IN MIN ● 90 ● 88 76.3 ● 75.9 73.6 ● 73.2 ● 100 LTC2206 LTC2207 TYP MAX MIN TYP MAX 100 100 100 100 100 90 100 100 100 100 100 100 ...

Page 5

... 160µA 0.01 O ● 1.6mA 0.10 0.4 O – –200µA 2. 1.60mA 0 –200µA 1. 1.60mA 0.1 O LTC2206 LTC2207 TYP MAX MIN TYP MAX 3.3 3.465 3.135 3.3 3.465 0.2 0.2 3.6 0.5 3.6 220 265 273 325 725 875 900 1,073 UNITS V ppm/°C mV/ V Ω UNITS V V Ω ...

Page 6

... SAMPLE with differential drive. P – – 3 22076 TD01 MAX UNITS 105 MHz 500 ns 500 ns 500 ns 500 0 ...

Page 7

... FREQUENCY (MHz) LTC2207: SFDR vs Input Level 15MHz, PGA = 0, IN Dither “On”, 105Msps 140 120 100 –80 –70 –60 –50 –40 –30 -20 –10 ...

Page 8

... PGA = 0, Dither “On”, 105Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 FREQUENCY (MHz) LTC2207: SFDR vs Input Level 140MHz, PGA = 1, IN Dither “On”, 105Msps 140 130 120 110 100 – ...

Page 9

... LTC2207: 5MHz SNR and SFDR vs Sample Rate, 105Msps 105 100 SAMPLE RATE (Msps) LTC2207: SNR and SFDR vs Duty Cycle, 105Msps 110 100 DUTY CYCLE (%) LTC2207: SFDR (HD2 and HD3) vs Input Frequency, 105Msps 105 100 ...

Page 10

... LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS LTC2206: INL, 80Msps 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0 8192 16384 24576 32768 40960 49152 57344 OUTPUT CODE 22076 G26 LTC2206: 128K Point FFT 4.93MHz, –1dBFS, PGA = 0, IN 80Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 – ...

Page 11

... FREQUENCY (MHz) LTC2207/LTC2206 LTC2206: 64K Point 2-Tone FFT 14.8MHz and 18.6MHz, IN –15dBFS, PGA = 0, 80Msps 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 ...

Page 12

... LTC2207/LTC2206 TYPICAL PERFORMANCE CHARACTERISTICS LTC2206: SFDR vs Input Level 140.2MHz, PGA = 0, IN Dither “Off”, 80Msps 130 120 110 100 –20 –10 –80 –70 –60 –50 –40 –30 INPUT LEVEL (dBFS) 22076 G44 LTC2206: 64K Point FFT 250.2MHz, –1dBFS, ...

Page 13

... G53 Normalized Full-Scale Error vs Temperature, Internal Reference, 5 Units 1.001 1.000 0.999 0.998 0.997 0.996 0.995 85 –40 – TEMPERATURE (°C) LTC2207/LTC2206 SFDR vs Analog Input Common Mode Voltage, 10MHz and 70MHz, –1dBFS, PGA = 0 110 105 10MHz 100 95 70MHz 0.5 ...

Page 14

... LTC2207/LTC2206 PIN FUNCTIONS SENSE (Pin 1): Reference Mode Select and External Reference Input. Tie SENSE 2.5V bandgap reference. An external reference of 2.5V or 1.25V may be used; both reference values will set a full scale ADC range of 2.25V (PGA = 0). V (Pin 2): 1.25V Output. Optimum voltage for input com- CM mon mode ...

Page 15

... DIFFERENTIAL ADC INPUT CONTROL REFERENCE LOW JITTER LOGIC CLOCK DRIVER + – ENC ENC SHDN PGA RAND MODE Figure 1. Functional Block Diagram LTC2207/LTC2206 V DD FIFTH PIPELINED ADC STAGE ADC STAGE GND CORRECTION LOGIC AND SHIFT REGISTER OV CLKOUT+ CLKOUT– OF D15 OUTPUT D14 DRIVERS • ...

Page 16

... LTC2207/LTC2206 OPERATION DYNAMIC PERFORMANCE Signal-to-Noise Plus Distortion Ratio The signal-to-noise plus distortion ratio [S/(N+D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band lim- ited to frequencies above DC to below half the sampling frequency ...

Page 17

... APPLICATIONS INFORMATION CONVERTER OPERATION The LTC2207/LTC2206 are CMOS pipelined multistep con- verters with a front-end PGA. As shown in Figure 1, the con- verter has fi ve pipelined ADC stages; a sampled analog input will result in a digitized value seven cycles clock later (see the Timing Diagram section). The analog input is differential for improved common mode noise immunity and to maximize the input range ...

Page 18

... LTC2207/LTC2206 APPLICATIONS INFORMATION SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2207/ LTC2206 CMOS differential sample and hold. The differ- ential analog inputs are sampled directly onto sampling capacitors (C ) through NMOS transitors. The SAMPLE capacitors shown attached to each input (C the summation of all other capacitance associated with each input ...

Page 19

... The LTC2207/ LTC2206 do not require any input fi lter to achieve data sheet specifi cations; however, no fi ltering will put more stringent noise requirements on the input drive circuitry ...

Page 20

... Reference Operation Figure 6 shows the LTC2207/LTC2206 reference circuitry consisting of a 2.5V bandgap reference, a programmable gain amplifi er and control circuit. The LTC2207/LTC2206 have three modes of reference operation: Internal Refer- ence, 1.25V external reference or 2.5V external reference. To use the internal reference, tie the SENSE pin to V use an external reference, simply apply either a 1 ...

Page 21

... LTC2207/LTC2206 V DD LTC2207/ LTC2206 TO INTERNAL ADC CLOCK DRIVERS 1. 1. Figure 8a. Equivalent Encode Input Circuit + ENC V = 1.6V THRESHOLD LTC2207/ – 1.6V ENC LTC2206 0.1µF 22076 F09 Figure 9. Single-Ended ENC Drive, Not Recommended for Low Jitter LTC2207/ LTC2206 22076 F10 22076 F08a 22076fa 21 ...

Page 22

... PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin must be or 2/3V connected to 1/3V DD The lower limit of the LTC2207/LTC2206 sample rate is determined by droop of the sample and hold circuits. The pipelined architecture of this ADC relies on storing analog for DD signals on small valued capacitors. Junction leakage will discharge the capacitors. The specifi ...

Page 23

... As with all high speed/high resolution converters, the digi- tal output loading can affect the performance. The digital outputs of the LTC2207/LTC2206 should drive a minimum capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as a ALVCH16373 CMOS latch ...

Page 24

... OV OGND and OV Internal Dither The LTC2207/LTC2206 are 16-bit ADCs with a very lin- ear transfer function; however, at low input levels even slight imperfections in the transfer function will result in unwanted tones. Small errors in the transfer function are usually a result of ADC element mismatches ...

Page 25

... APPLICATIONS INFORMATION PC BOARD FPGA CLKOUT OF D15/D0 LTC2207/ LTC2206 D14/D0 D2/D0 D1/D0 D0 Figure 14. Descrambling a Scrambled Digital Output LTC2207/LTC2206 D15 D14 • • • 22076 F14 22076fa 25 ...

Page 26

... LTC2207/LTC2206 APPLICATIONS INFORMATION Grounding and Bypassing The LTC2207/LTC2206 require a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. The pinout of the LTC2207/LTC2206 has been optimized for a fl owthrough layout so that the interaction between inputs and digital outputs is minimized ...

Page 27

... APPLICATIONS INFORMATION Silkscreen Top LTC2207/LTC2206 Top Side 22076fa 27 ...

Page 28

... LTC2207/LTC2206 APPLICATIONS INFORMATION Inner Layer 2 Inner Layer 4 28 Inner Layer 3 Inner Layer 5 22076fa ...

Page 29

... APPLICATIONS INFORMATION Bottom Side LTC2207/LTC2206 Silkscreen Bottom 22076fa 29 ...

Page 30

... LTC2207CUK DC918C-B LTC2207CUK DC918C-C LTC2206CUK DC918C-D LTC2206CUK DC918C-E LTC2205CUK DC918C-F LTC2205CUK DC918C-G LTC2204CUK DC918C-H LTC2207CUK-14 DC918C-I LTC2207CUK-14 DC918C-J LTC2206CUK-14 DC918C-K LTC2206CUK-14 DC918C-L LTC2205CUK-14 See Web site for ordering details or contact local sales. 30 RESOLUTION SPEED INPUT FREQUENCY 16-Bit 105Msps 1MHz to 70MHz 16-Bit ...

Page 31

... Plastic QFN (7mm × 7mm) (Reference LTC DWG # 05-08-1704) 0.70 ±0.05 5.15 ±0.05 6.10 ±0.05 7.50 ±0.05 (4 SIDES) PACKAGE OUTLINE 0.75 ± 0. 0.115 5.15 ± 0.10 (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2207/LTC2206 TYP 47 48 0.40 ± 0.10 1 PIN 1 2 CHAMFER (UK48) QFN 1103 0.25 ± 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD 22076fa ...

Page 32

... ADC, Lowest Noise LTC2203 16-Bit, 25Msps, 3.3V ADC, Lowest Noise LTC2204 16-Bit, 40Msps, 3.3V ADC LTC2205 16-Bit, 65Msps, 3.3V ADC LTC2206 16-Bit, 80Msps, 3.3V ADC LTC2207 16-Bit, 105Msps, 3.3V ADC LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs LTC2220 12-Bit, 170Msps ADC LTC2220-1 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs LTC2224 12-Bit, 135Msps, 3 ...

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