LTC4255 LINER [Linear Technology], LTC4255 Datasheet
LTC4255
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LTC4255 Summary of contents
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... External switches and current sense resistors allow easy scaling of current and power dissipation levels and pro- vide the maximum protection against voltage and current spikes. The LTC4255 is available in the 28-pin SSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation trademark of Philips Electronics N.V. ...
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... Relay Driver Output Voltage RELAY1-4 (Note 5) ...... DGND –0.3V to DGND + 15V Analog Voltages SENSE1-4 ............................... V OUT1-4 .................................. V Operating Temperature Range LTC4255C ............................................... Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 C ELECTRICAL CHARACTERISTICS temperature range, otherwise specifications are at T SYMBOL PARAMETER ...
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... Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Figure 1 (Notes 3, 4) Note 3: Guaranteed by design, not subject to test. Note 4: Values referred to V Note 5: A Zener diode clamps the relay drivers at 18V (RELAY 1-4). LTC4255 MIN TYP MAX UNITS 0.8 V 2.4 V ...
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... LTC4255 W U TYPICAL PERFOR A CE CHARACTERISTICS (Relays Off 1.290 1.280 1.270 1.260 1.250 1.240 10.8 11.3 11.8 12.3 12.8 13.3 V (V) CC 4255 G01 I vs Temperature (Relays On 12V CC 9.5 9.4 9.3 9.2 9.1 9.0 8.9 8.8 –50 – 100 TEMPERATURE ( C) 4255 G04 OUT 160 140 ...
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... Relay Driver Output Low Voltage ( Temperature OLR 0.170 I = 50mA RELAY 0.165 0.160 0.155 0.150 0.145 0.140 0.135 0.130 –50 – TEMPERATURE ( C) LTC4255 I vs Temperature GATE –44 GATE GATE EE –46 –48 –50 –52 –54 –56 –58 75 100 –50 –25 0 ...
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... LTC4255 CTIO S FAULT (Pin 1): Open-Drain FAULT Output. Pulls low when a short-circuit or open circuit fault occurs. The signal can be used to generate a fault condition interrupt to the host controller eliminating the need for continuous software polling. SCL (Pin 2): Serial Interface Clock Input. It requires a resistor or current source that pulls supply that is less than 6V ...
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... C1: Power_OK for Port 2. Logic high indicates switch 2 is on. C2: Power_OK for Port 3. Logic high indicates switch 3 is on. C3: Power_OK for Port 4. Logic high indicates switch 4 is on. C4: Reserved. Logic high. C5: Reserved. Logic low. C6: Reserved. Logic low. C7: Reserved. Logic low. LTC4255 OCD , in AC Charac- OCD , ...
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... LTC4255 U U REGISTER DEFI ITIO S Register 4: Status Register 2 (Read Only) D0: Current Limit Fault Status for Port 1. Logic high indicates a short-circuit has been detected on Port 1. D1: Current Limit Fault Status for Port 2. Logic high indicates a short-circuit has been detected on Port 2. D2: Current Limit Fault Status for Port 3. Logic high indicates a short-circuit has been detected on Port 3 ...
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... CONTROL BYTE Figure 6. Writing to the Control Register Only R/W ACK ACK BY ACK BY SLAVE SLAVE FRAME 2 CONTROL BYTE Figure 7. Clearing the FAULT Signal LTC4255 ACK ACK STOP BY MASTER. INTERNAL DATA LATCHES UPDATED FRAME 3 SETUP BYTE A1 A0 ...
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... LTC4255 DIAGRA S SCL SDA AD4 AD3 AD2 AD1 AD0 0 1 START BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE SCL SDA 0 AD4 AD3 AD2 AD1 AD0 1 START BY MASTER SERIAL BUS ADDRESS BYTE 10 R/W ACK ACK BY ACK BY SLAVE ...
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... At the same time, the GATE1 pin will be pulled low current source, the FET will turn off, and the Power_OK bit will be cleared. AO ACK STOP BIT FET TURNS ON POWER LTC4255 , the Power_OK EE AO ACK E 4255 F09 4255f 11 ...
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... LTC4255 U U APPLICATIO S I FOR ATIO Power-Up with No Load When a channel powers-up with no load, the initial sequence is the same as the normal case. When the V voltage is within the power good threshold, the Power_OK bit is set (point D, Figure 10) and the open-circuit enable delay timer started. The duration of the timer can be programmed via bits B6-B7 ...
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... FET on-time to off-time under a short-circuit condition STOP BIT FET CL TIMER EXPIRES CHANNEL LATCHES OFF LTC4255 ). This duty cycle is programmable via bit ACK BO STOP BIT FAULT CLEARED ...
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... A 100k resistor should be placed between the drains of the FETs and the OUT1-4 pins to limit the energy absorbed by the LTC4255 if the drains of the FETs exceed OUT1-4’s absolute maximum voltage rating. Also, if the FETs are not capable of safely absorbing this energy, high-speed ...
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... LTC DWG # 05-08-1640) 1.25 0. 5.3 – 5.7 0.65 BSC – 8 0.65 (.0256) BSC 0.22 – 0.38 (.009 – .015) LTC4255 4255 F13 9.90 – 10.50* (.390 – .413 7.40 – 8.20 (.291 – .323 2.0 (.079) 0.05 (.002) G28 SSOP 0802 ...
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... Negative Voltage Hot Swap Controller in SOT-23 LTC4300-1/LTC4300-2 Hot Swappable 2-Wire Bus Buffer Linear Technology Corporation 16 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 www.linear.com 12V 0 LTC4255 OUT1 SENSE2 GATE2 OUT2 SENSE3 GATE3 OUT3 SENSE4 GATE4 OUT4 100k 100k 100k 0. ...