MC100EL01D ON Semiconductor, MC100EL01D Datasheet

Gates (AND / NAND / OR / NOR) 5V ECL 4-Input

MC100EL01D

Manufacturer Part Number
MC100EL01D
Description
Gates (AND / NAND / OR / NOR) 5V ECL 4-Input
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC100EL01D

Product
MUX Gates
Logic Family
ECL
Number Of Gates
1
Number Of Lines (input / Output)
4 / 2
High Level Output Current
- 50 mA
Low Level Output Current
50 mA
Propagation Delay Time
0.33 ns
Supply Voltage (max)
+/- 5.7 V
Supply Voltage (min)
+/- 4.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SOIC-8 Narrow
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
No RoHS Version Available

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100EL01D
Manufacturer:
ON/安森美
Quantity:
20 000
Part Number:
MC100EL01DG
Quantity:
5 510
Part Number:
MC100EL01DG
Quantity:
5 510
MC10EL01, MC100EL01
5V ECL 4‐Input OR/NOR
Description
functionally equivalent to the E101 device with higher performance
capabilities. With propagation delays and output transition times
significantly faster than the E101, the EL01 is ideally suited for those
applications which require the ultimate in AC performance.
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 6
The MC10EL/100EL01 is a 4-input OR/NOR gate. The device is
The 100 series contains temperature compensation.
> 100 V Machine Model
with V
with V
For Additional Information, see Application Note AND8003/D
Oxygen Index: 28 to 34
230 ps Propagation Delay
ESD Protection: > 1 kV Human Body Model,
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL 94 V−0 @ 0.125 in,
Transistor Count = 46 devices
Pb−Free Packages are Available
EE
EE
Figure 1. Logic Diagram and Pinout Assignment
= −4.2 V to −5.7 V
= 0 V
D
D
D
D
0
1
2
3
1
2
3
4
CC
CC
= 4.2 V to 5.7 V
= 0 V
8
7
6
5
V
Q
Q
V
CC
EE
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
H = MC10
K = MC100
4M = MC10
2A = MC100
A = Assembly Location
CASE 506AA
CASE 948R
MN SUFFIX
*For additional marking information, refer to
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
8
(Note: Microdot may be in either location)
Application Note AND8002/D.
SOIC−8
8
DFN8
ORDERING INFORMATION
1
1
http://onsemi.com
8
1
8
1
HEL01
ALYWG
Publication Order Number:
ALYW
HL01
1
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
DIAGRAMS*
G
G
MARKING
4
8
1
8
1
MC10EL01/D
ALYWG
1
KEL01
ALYW
KL01
G
G
4

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MC100EL01D Summary of contents

Page 1

MC10EL01, MC100EL01 5V ECL 4‐Input OR/NOR Description The MC10EL/100EL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the E101 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E101, the EL01 ...

Page 2

Table 1. PIN DESCRIPTION PIN D0− Table 2. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input ...

Page 3

Table 3. 10EL SERIES PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage IH V Input LOW Voltage IL I Input ...

Page 4

Table 5. 100EL SERIES PECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage IH V Input LOW Voltage IL I Input ...

Page 5

... MC10EL01DG MC10EL01DR2 MC10EL01DR2G MC10EL01DT MC10EL01DTG MC10EL01DTR2 MC10EL01DTR2G MC10EL01MNR4 MC10EL01MNR4G MC100EL01D MC100EL01DG MC100EL01DR2 MC100EL01DR2G MC100EL01DT MC100EL01DTG MC100EL01DTR2 MC100EL01DTR2G MC100EL01MNR4 MC100EL01MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ ...

Page 6

Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...

Page 7

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 8

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 9

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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