MC100EP139 ON Semiconductor, MC100EP139 Datasheet

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MC100EP139

Manufacturer Part Number
MC100EP139
Description
2/4 / 4./5/6 Clock Generation Chip
Manufacturer
ON Semiconductor
Datasheet

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MC100EP139
Product Preview
Generation Chip
designed explicitly for low skew clock generation applications. The
internal dividers are synchronous to each other, therefore, the common
output edges are all precisely aligned. The device can be driven by
either a differential or single–ended ECL or, if positive power supplies
are used, LVPECL input signals. In addition, by using the V BB output,
a sinusoidal source can be AC coupled into the device. If a
single–ended input is to be used, the V BB output should be connected
to the CLK input and bypassed to ground via a 0.01 F capacitor.
dividers will only be enabled/disabled when the internal clock is
already in the LOW state. This avoids any chance of generating a runt
clock pulse on the internal clock when the device is enabled/disabled
as can happen with an asynchronous control. The internal enable
flip–flop is clocked on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the negative edge of
the clock input.
therefore, for systems which utilize multiple EP139s, the master reset
(MR) input must be asserted to ensure synchronization. For systems
which only use one EP139, the MR pin need not be exercised as the
internal divider design ensures synchronization between the 2/4 and
the 4/5/6 outputs of a single device. All V CC and V EE pins must be
externally connected to power supply to guarantee proper operation.
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
December, 1999 – Rev. 1
The MC100EP139 is a low skew 2/4, 4/5/6 clock generation chip
The common enable (EN) is synchronous so that the internal
Upon startup, the internal flip–flops will attain a random state;
2/4,
For Additional Information, See Application Note AND8003/D
Oxygen Index 28 to 34
50ps Output–to–Output Skew
PECL mode: 3.0V to 5.5V V CC with V EE = 0V
ECL mode: 0V V CC with V EE = –3.0V to –5.5V
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
Q Output will default LOW with inputs open or at V EE
ESD Protection: >2KV HBM, >100V MM
V BB Output
New Differential Input Common Mode Range
Moisture Sensitivity Level 2
Flammability Rating: UL–94 code V–0 @ 1/8”,
Transistor Count = 758 devices
Semiconductor Components Industries, LLC, 1999
4/5/6 Clock
1
*For additional information, see Application Note
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
MC100EP139DT
MC100EP139DTR2
MC100EP139DW
MC100EP139DWR2
AND8002/D
CASE 948E
DT SUFFIX
TSSOP–20
ALYW
Device
KEP
139
ORDERING INFORMATION
MARKING DIAGRAM
http://onsemi.com
Package
TSSOP
TSSOP
SOIC
SOIC
Publication Order Number:
A
WL = Wafer Lot
YY = Year
WW = Work Week
= Assembly Location
MC100EP139
DW SUFFIX
CASE 751D
AWLYWW
2500 Tape/Reel
2500 Tape/Reel
SO–20
MC100EP139/D
75 Units/Rail
38 Units/Rail
Shipping

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MC100EP139 Summary of contents

Page 1

... Product Preview 2/4, 4/5/6 Clock Generation Chip The MC100EP139 is a low skew 2/4, 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single– ...

Page 2

... Divide by 4 DIVSELb0 DIVSELb1 Q2:3 OUTPUTS 0 0 Divide Divide Divide Divide by 5 DIVSELa CLK CLK EN MR DIVSELb0 DIVSELb1 Figure 2. Logic Diagram MC100EP139 CLK PIN DESCRIPTION ...

Page 3

... Thermal Resistance (Junction–to–Case) T sol Solder Temperature (< Seconds: 245 C desired) * Maximum Ratings are those values beyond which damage to the device may occur. { Use for inputs of same package only. MC100EP139 Figure 3. Timing Diagram t RR Figure 4. Timing Diagram Parameter Continuous Surge ...

Page 4

... 3.0V 0V, all other pins floating. 5. All loading with 50 ohms –2.0 volts. 6. Input and output parameters vary 1:1 with MC100EP139 – Min ...

Page 5

... Input Voltage Swing (Diff Reset Recovery Time t pw Minimum Pulse Width CLK MR 10. F max guaranteed for functionality only and V OH levels are guaranteed at DC only. 11. Skew is measured between outputs under identical transitions. MC100EP139 0.5V 0V) (Note 9.) – Min Typ Max Min Typ ...

Page 6

... L PIN 1 IDENT 1 0.15 (0.006 –V– 0.100 (0.004) –T– SEATING PLANE MC100EP139 PACKAGE DIMENSIONS TSSOP–20 DT SUFFIX CASE 948E–02 ISSUE A NOTES Í Í Í Í Í Í Í Í B –U– ...

Page 7

... MC100EP139 PACKAGE DIMENSIONS 20 PIN PLASTIC SOIC PACKAGE CASE 751D– 20X 0. SEATING PLANE e 18X A1 T http://onsemi.com SO–20 DW SUFFIX ISSUE F q NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSION ...

Page 8

... Email: ONlit–asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–8549 Phone: 81–3–5487–8345 Email: r14153@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC100EP139/D ...

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