mc100lvep11 ON Semiconductor, mc100lvep11 Datasheet
mc100lvep11
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mc100lvep11 Summary of contents
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... MC10LVEP11, MC100LVEP11 2.5V / 3.3V ECL 1:2 Differential Fanout Buffer Description The MC10/100LVEP11 is a differential 1:2 fanout buffer. The device is pin and functionally equivalent to the EP11 device. With AC performance the same as the EP11 device, the LVEP11 is ideal for applications requiring lower voltage. Single−ended CLK input operation is limited ...
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Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability ...
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Table 3. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out T Operating Temperature Range A T Storage Temperature ...
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Table 4. 10LVEP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage Common Mode IHCMR Range (Differential Configuration) (Note 4) I ...
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Table 6. 10LVEP DC CHARACTERISTICS, NECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 10 Output LOW Voltage (Note 10 Input HIGH Voltage (Single−Ended) IH (Note 11) V Input LOW Voltage (Single−Ended) ...
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Table 8. 100LVEP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note 17 Output LOW Voltage (Note 17 Input HIGH Voltage (Single−Ended) IH (Note 18) V Input LOW Voltage (Single−Ended) ...
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Table 10. AC CHARACTERISTICS Symbol Characteristic f Maximum Frequency (Figure 2) max t , Propagation Delay PLH t (Differential Configuration) PHL CLK Within Device Skew SKEW Device to Device Skew (Note 25) t CLOCK Random Jitter ...
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... MC10LVEP11DT MC10LVEP11DTG MC10LVEP11DTR2 MC10LVEP11DTR2G MC10LVEP11MNR4 MC10LVEP11MNR4G MC100LVEP11D MC100LVEP11DG MC100LVEP11DR2 MC100LVEP11DR2G MC100LVEP11DT MC100LVEP11DTG MC100LVEP11DTR2 MC100LVEP11DTR2G MC100LVEP11MNR4 MC100LVEP11MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/ ...
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Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
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... C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004) ...
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K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) −T− D SEATING G PLANE PACKAGE DIMENSIONS TSSOP−8 ...
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... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...