pdsp16510a Zarlink Semiconductor, pdsp16510a Datasheet

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... GND WORD DIS DOS INEN AUX15:0 R15:0 PDSP16510 D15:0 I15:0 DEN DAV S3:0 DEF GND RESET PDSP16510A PDSP16510A Stand Alone FFT Processor ISSUE 4.4 DATA INPUT 3 TERM WINDOW OPERATOR COEFFICIENT WORKSPACE WORKSPACE ROM RAM FOUR DATA PATHS RESULT OUPUT Fig. 1. Block Diagram CLK ...

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... PDSP16510A N D9 D10 D12 M D8 D11 GND LFLG F VDD R10 R11 PIN FUNC PIN 1 VDD 23 2 GND I10 28 7 VDD 29 8 I11 30 9 GND ...

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... RAM in normal sequential order, processed, and then dumped in the correct order. With real only input data the processing time can approximately be PDSP16510A halved for a given transform size. Two real inputs then replace a single complex input, and are processed in parallel. ...

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... PDSP16510A spaced frequencies are to be detected, and one is of smaller magnitude than the other. It does, however, reduce the actual frequency resolution, and the Hamming window may then be preferable. Data in and out of the device is represented by 16 bit real and imaginary components, with 16 bit sine and cosine values contained in an internal ROM ...

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... The internal RAM organisation is shown in Fig should be SAMPLE CLOCK GND WEN IMAG' REAL RS FFT O/P BUFFER SYSTEM CLOCK LOAD IN LAST PASS PDSP16510A TRANS- FORM WORKSPACE FFT DATA PATH LOAD POWER ON RESET 510 PARAMETERS GND WS RES AUX I PDSP16540 ...

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... PDSP16510A noted that the amount of overlap between I/O transfers and transforms is completely under the control of the system, since an input enable signal (INEN) and an output enable (DEN) can be used to initiate transfers. In the 1024 point mode there is insufficient workspace for input and output buffering in addition to working memory. The device is then configured in a mode with separate load, transform and dump operations ...

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... Bit 12 in the Control Register is reset in the SINGLE device mode, the edge activated operation will still be possible. With all but 256 point PDSP16510A complex transforms, the single device edge mode of opera- tion is identical to that of a multiple device system. With 256 ...

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... PDSP16510A with a number of DOS strobes (see "user notes - stopping DOS") once a transform is complete in order to transfer data to the output pins. DAV will not go active until this priming has occurred. The state of the DEN input at the end of a transform is used to control the transition of the active going edge of the DAV output with respect to the DOS strobes ...

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... DEN goes in- active, then both the (4) O Scale Tag Value 16510A,A0,B0,C0 Symbol PDSP16510A T VI O/P 2 O/P N Scale Tag Value Min Max Units ...

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... PDSP16510A AUX O/P PDSP16510 DIN S3:0 SYSTEM CLOCK Fig. 7. Host Controlled System data and scale tag outputs will go high impedance after the delay shown in Table 3. Valid transformed data is actually available within the device from DAV going active until INEN again goes active, and a new set of data is loaded. The output tristate drivers, however, normally go high impedance when DAV goes in- active once a dump operation has been completed ...

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... For non continuous transforms the peak rate is limited by the system clock rate and the factor , F, 1024 COMPLEX 256 COMPLEX 0% 50% 75% 0% 50% 75% 12.3 6.1 3.0 6.8 3.4 1.7 PDSP16510A Clock Periods COMP 420 COMP 624 COMP 816 COMP 3907 REAL 816 REAL 1032 REAL 4699 ...

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... PDSP16510A given previously. The time taken to dump the transformed data must be no more than the load time, if continuous inputs are to be supported and I/O operations are concurrent with transforms. With block overlapping the dump time must be reduced to the time taken to load the partial block. This dump time must include four extra DOS strobes needed to prime the output circuitry when a transform is complete ...

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... A further change to the output circuitry ensures that the output buffer is primed even though DEN is not active. The first word, however, only progresses as far as the final output latch. The output bus is not enabled, and address increments do not TRANSFORM A1 DUMP A LOAD B1 TRANS LOAD C1 PDSP16510A TRANSFORM C1 13 ...

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... PDSP16510A occur, until DEN is finally received. This modification to the internal control logic ensures that the output buffer does not impose unnecessary gaps between consecutive transforms. These gaps would, in turn, force the required DOS frequency to be greater than the DIS frequency ( or greater than twice or four times the frequency with 50% and 75% overlaps ) ...

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... If 50% or 75% overlaps are needed from a single source of real data, the device always expects blocks to be simultaneously loaded. An external FIFO is then needed to supply data to the real inputs after a delay of one block. Each block is thus loaded twice, PDSP16510A 15 ...

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... PDSP16510A firstly through the Auxiliary inputs and then through the Real inputs. BIT 10:9 These bits define a single device system, or one of three multiple device possibilities. The choice between the first and second multiple device mode is dependent on the transform size and the sampling rate needed. The third mode should only be used when overlapped multiple transforms with less than 1024 points are to be performed simultaneously ...

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... To avoid this loss partitions are usually overlapped by 50% or 75%, which might, at first sight, remove the need to average successive transforms. If non-windowed Highest Mid-Point Overall Side Lobe Loss dB Loss dB -13 3.92 3.92 -43 1.78 3.1 -70 1.25 3.35 -69 1.02 3.55 -58 1.1 3.47 -67 1.13 3.45 PDSP16510A 6dB Overlap Correlation Bandwidth 75% 50% 1. 1.81 70.7 23.5 2.17 60.2 11.9 2.39 53.9 7.4 2.35 56.7 9 1.81 57.2 9.6 17 ...

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... PDSP16510A Arithmetic Accuracy Max Tone WRT Noise 16 bit,unconditional 60 scaling 24 bit arithmetic with unconditional scaling bit inputs 16 bit inputs with 74 PDSP16510 block FP Full 32 bit Floating point with 16 bit inputs 93 Table 8. Comparative Dynamic Range Measurements transforms are overlapped by 75% or 50%, then 75% or 50% of the data will be correlated ...

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... DOS. If DEN is active at this point, or the device is programmed in any multiple device mode, then DAV will remain inactive. PDSP16510A (3.2) Accessing the RAM at this point At this moment, when DAV has been made active before data appears on the output pins, data is not yet in the output buffer ...

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... PDSP16510A (4) OUTPUT SCENARIOS Considering the above sequence, therefore, some single device situations can now be explained : (4.1) DOS is continuously present, but DEN is inactive (Transform size less than 1024) In this case, when the transform is complete, as the device is programmed as a single device and DEN is inactive, DAV will be made active. Even though DOS is running, the status of DAV at this point does not rely on it ...

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... Current is defined as positive into the device. ELECTRICAL CHARACTERISTICS Operating Conditions (unless otherwise state) PDSP16510A C0 Tamb = PDSP16510A B0 Tamb = - PDSP16510A A0 Tamb = - +125 C. Vcc = 5.0v Characteristic Output high voltage Output low voltage Input high voltage Input low voltage Input leakage current ...

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... PDSP16510A ORDERING INFORMATION PDSP16510A C0 AC PDSP16510A C0 GC PDSP16510A B0 AC PDSP16510A B0 GC PDSP16510A A0 AC PDSP16510A A0 GC PDSP16510A/MA/GCPR 22 ( Commercial -PGA Package ) ( Commercial -Leaded Chip Carrier ) ( Industrial - PGA Package ) ( Industrial - Leaded Chip Carrier ) ( Military - PGA Package ) ( Military - Leaded Chip Carrier ) ( Military - Screened Leaded Chip Carrier. See separate datasheet for details) ...

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