1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Function Table
Pinout
Features
• Complies with ANSI/TIA/EIA-644-A LVDS standard
• LVDS receiver inputs accept LVPECL signals
• Low jitter 660 Mbps fully differential data path
• Bus-Terminal ESD exceeds 2kV
• Single +3.3 V supply voltage operation
• Receiver Differential Input Voltage Threshold < ±100 mV
• Receiver open-circuit failsafe
• Low-Voltage Differential Signaling with typical Output
• Typical Propagation Delay Times of 1.5ns
• Typical Power Dissipation of 20mW @ 200MHz
• Outputs are High Impedance with V
• Industrial Temperature Range: –40 C to 85 C
• Package: 6-pin space-saving SOT-23 (T)
H = high level; L = low level; ? = indeterminate
Logic Diagram
Voltages of 350mV into:
– 100-ohm Load (PI90LV03)
– 50-ohm Load (PI90LVB03)
-50m
V
V
V
V
D I
A
B
D I
D I
<
n I
=
O
>
V
u p
p
V
–
D I
0 5
1
2
n e
0 5
GND
A
s t
<
m
–
m
A
B
V
V
0 5
V
B
m
V
1
2
3
6
5
4
CC
V DD
Y
Z
5
4
< 1.5V
O
V
Y
t u
H
H
L
-
?
u p
Y
Z
V
s t
Z
1
Description
PI90LV03 and PI90LVB03 are single LVDS Repeaters that use low-
voltage differential signaling (LVDS) to support data rates up to 660
Mbps. The PI90LVB03 features high-drive output. These products
are designed for applications requiring high-speed, low-power
consumption, low-noise generation, and a small package.
The LVDS Repeaters take an LVDS input signal and provide an LVDS
output to address various interface logic requirements such as
signal isolation, repeater, stub length, and Optical Transceiver
Modules. In many large systems, signals are distributed across
backplanes, and the distance between the transmission line and the
unterminated receivers are one of the limiting factors for system
speed. The buffers can be used to reduce the ‘stub length’ by
strategic device placement along the trace length. They can improve
system performance by allowing the receiver to be placed very close
to the main transmission line or very close to the connector on the
card. Longer traces to the LVDS receiver can then be placed after the
buffer.
The buffer’s wide input dynamic range enables them to receive
differential signals from LVPECL and LVDS sources. The devices
can be used as compact high-speed serial translators between
LVPECL and LVDS data lines. The differential translation provides
a simple way to mix and match Optical Transceiver ICs from various
vendors without redesigning the interfaces.
Applications
The PI90LV03 and PI90LVB03 provide differential translation
between LVDS and PECL devices for high-speed, point-to-point
interface and telecom applications:
Figure 1. High-Speed Differential Cable Repeater Application
– ATM
– SONET/SDH
– Switches
– Routers
– Add-Drop Multiplexers
T X
R T = Z O
Z O
LVDS Repeater
PI90LV03/PI90LVB03
SOTiny
®
Z O
LVDS Repeater
R T = Z O
PS8660
Any LvDS R X
02/25/03