SSM2163 Analog, SSM2163 Datasheet
SSM2163
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SSM2163 Summary of contents
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... DCA V IN8 DCA: DIGITALLY CONTROLLED ATTENUATOR The SSM2163 can be operated from single (+ + dual ( supplies, and is housed in 28-pin plastic DIP and SOIC packages. The SSM2163 is an ideal companion product to the Analog Devices family of stereo codecs in high performance multi- media systems requiring mixing of multiple signals ...
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... SSM2163–SPECIFICATIONS ELECTRICAL SPECIFICATIONS Parameter AUDIO PERFORMANCE Noise Headroom Total Harmonic Distortion Plus Noise ANALOG INPUT Input Impedance VOLUME CONTROL Step Size Gain Error Gain Match Error Mute Attenuation ANALOG OUTPUT Output Impedance Output Current Minimum Resistive Load Maximum Capacitive Drive ...
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... pF and t are measured from the final negative transition to the idle Figure 1. Three-Wire Mode Timing Diagram –3– SSM2163 Typ Max Units 160 ...
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... SSM2163 1 CLK 0 1 DATA WRITE CLK DATA WRITE 0 1 LOAD 0 1 SDO Figure 2. Four-Wire Mode Timing Diagram –4– REV. 0 ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2163 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... Function 1 DGND Digital Ground Digital Negative Supply DATA OUT Serial data output clocked on positive clock edge. Connect DATA OUT to DATA IN pin to daisy-chain multiple SSM2163s. Output levels are Digital Positive Supply Audio Signal Input 1. IN1 6 NC (Shield) Shield Pin. Should be tied to AGND to minimize crosstalk. ...
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... –80 – –100 –110 –120 –130 –140 Figure 7. (THD+ kHz Tone at 0 dBu (4k-Point FFT) –7– SSM2163 + 0.0 0.002 0.004 0.006 0.008 0.010 THD – % Figure 6. THD Distribution 0dBu ...
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... SSM2163 0dBu 0dB V LPF = 22kHz R = 100k 0 + 0.010 0.001 20 100 1k FREQUENCY – Hz Figure 8. THD+N vs. Frequency 0dBu 0dB V LPF = 22kHz 100k + 0.1 0.010 0.001 0.005 100 1k 20 FREQUENCY – Hz Figure 9. THD+N vs. Frequency – Single Supply ...
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... Figure 18. Output Channel Separation vs. Frequency 10k 20k Figure 19. Supply Current vs. Supply Voltage –9– SSM2163 = 5V 50mS = + 100 20mV Figure 17. Broadband Noise CHANNEL 1 0dBu 0dB V LPF = 22kHz = 100k ...
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... Serial Data Control Inputs The SSM2163 provides a simple 3- or 4-wire serial interface (Figures 22 and 23). Data is input on the DATA IN pin, while CLK is the serial clock. Data can be shifted into the SSM2163 clock rates MHz. OUTPUT SUMMING The shift register clock, CLK, is enabled when the WRITE ...
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... SSM2163 package as possible (Figures 22a, 22b, 22c, power supply connections). Single Supply Operation The SSM2163 will operate with a single power supply +14 V. Single supply operation simplifies design and reduces system cost in multimedia applications, battery powered systems, and similar designs. The SSM2163 provides about headroom (to 1% THD+N) when operating from a single +5 V supply ...
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... Supply Decoupling Optimizing the performance of the SSM2163, or any low noise device, requires careful attention to power supply decoupling. Since the SSM2163 can operate from a single +5 V supply, it seems convenient to simply tap into the digital logic power supply. Unfortunately, the logic supply is often a switch-mode design, which generates noise in the 20 kHz to 1 MHz range ...
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... SSM2163s can be paralleled to provide additional channels. A typical circuit is shown in Figure 26, which combines two SSM2163s to form a 16-input, 2-output mixer. An SSM2135 dual audio op amp sums the outputs of each of the SSM2163s. With this system, any of the 16 inputs can be mixed into either or both of the output channels. ...
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... The SSM2163, on the other hand, requires data in MSB format. A BYTESWAP routine swaps the order of the bits before transmission. The SSM2163 requires the Chip Select to go low at the begin- ning of the serial data transfer. After each 8 bits (either address or attenuation value) are transmitted, Chip Select must go high to latch data into the appropriate register. Chip Select is controlled by the 80C51’ ...
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... END The subroutine begins by setting appropriate bits in the Serial Control register to configure the serial port for Mode 0 operation. Next the SSM2163’s Chip Select input is set low to enable the SSM2163. The input channel address is obtained from memory location INPUT_ADDR, adjusted to compensate for the 80C51’ ...
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... P1.6 is then set or reset based on the carry bit, and Port P1.5 is strobed low and then high to create a clock pulse. After eight loops, the value will have been sent to the SSM2163. Note that all eight bits should be sent, even though only six bits are significant ...