sy100s834lzitr Micrel Semiconductor, sy100s834lzitr Datasheet

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sy100s834lzitr

Manufacturer Part Number
sy100s834lzitr
Description
Sy100s834/l ?1, ?2, ?4 Or ?2, ?4, ?8 Clock Generation Chip
Manufacturer
Micrel Semiconductor
Datasheet
Micrel, Inc.
Notes:
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
Precision Edge is a registered trademark of Micrel, Inc.
M9999-032206
hbwhelp@micrel.com or (408) 955-1690
FEATURES
TRUTH TABLE
PIN NAMES
F
3.3V and 5V power supply options
50ps output-to-output skew
Synchronous enable/disable
Master Reset for synchronization
Internal 75K input pull-down resistors
Available in 16-pin SOIC package
SEL
CLK
H
L
CLK
F
EN
MR
V
Q
Q
Q
ZZ
Z
X
SEL
BB
0
1
2
Pin
Q
Divide by 2
Divide by 1
0
Outputs
EN
H
L
X
Differential Clock Inputs
Function Select
Synchronous Enable
Master Reset
Reference Output
Differential 1 or 2 Outputs
Differential 2 or 4 Outputs
Differential 4 or 8 Outputs
Q
Divide by 4
Divide by 2
1
MR
Outputs
H
L
L
Function
Divide
Hold Q
Reset Q
Function
Q
Divide by 8
Divide by 4
2
0–2
Outputs
0–2
( 1, 2, 4) OR ( 2, 4, 8)
CLOCK GENERATION CHIP
1
skew clock generation applications. The internal dividers
are synchronous to each other, therefore, the common
output edges are all precisely aligned. The devices can
be driven by either a differential or single-ended ECL or,
if positive power supplies are used, PECL input signal.
In addition, by using the V
can be AC-coupled into the device. If a single-ended
input is to be used, the V
to the CLK input and bypassed to ground via a 0.01 F
capacitor. The V
switching reference for the input of the SY100S834/L
under single-ended input conditions. As a result, this pin
can only source/sink up to 0.5mA of current.
what clock generation chip function is. When FS
is LOW, SY100S834/L functions as a divide by 2, by 4
and by 8 clock generation chip. However, if FS
is HIGH, it functions as a divide by 1, by 2 and by 4
clock generation chip. This latter feature will increase
the clock frequency by two folds.
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
4, 8) clock generation chip designed explicitly for low
DESCRIPTION
The SY100S834/L is low skew ( 1, 2, 4) or ( 2,
The Function Select (F
The common enable (EN) is synchronous so that the
Upon start-up, the internal flip-flops will attain a random
BB
output is designed to act as the
BB
SEL
BB
output should be connected
) input is used to determine
output, a sinusoidal source
Precision Edge
SY100S834L
Rev.: G
Issue Date: March 2006
Precision Edge
SY100S834
Precision Edge®
SY100S834L
SY100S834
Amendment: /0
EL
EL
input
input
®
®

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sy100s834lzitr Summary of contents

Page 1

Micrel, Inc. FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors Available in 16-pin SOIC package TRUTH TABLE CLK ...

Page 2

... SY100S834ZC Z16-2 (1) SY100S834ZCTR Z16-2 SEL SY100S834LZC Z16-2 (1) SY100S834LZCTR Z16-2 SY100S834ZI Z16-2 (1) SY100S834ZITR Z16-2 SY100S834LZI Z16-2 BB (1) SY100S834LZITR Z16-2 (2) SY100S834ZG Z16-2 EE (1, 2) SY100S834ZGTR Z16-2 (2) SY100S834LZG Z16-2 (1, 2) SY100S834LZGTR Z16-2 Notes: 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. 2 Precision Edge® ...

Page 3

Micrel, Inc. DC ELECTRICAL CHARACTERISTICS (Min (Max.); Symbol Parameter I Power Supply Current EE V Output Reference Voltage -1. Input HIGH Current IH Note: 1. Parametric values specified ...

Page 4

Micrel, Inc. TIMING DIAGRAM CLK SEL SEL The EN signal will freeze the internal clocks to the flip-flops on the first ...

Page 5

Micrel, Inc. 16-PIN SOIC .150" WIDE (Z16-2) MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA + 1 (408) 944-0800 TEL The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no ...

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