YMF724 ETC, YMF724 Datasheet
YMF724
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YMF724 Summary of contents
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... YMF724F OVERVIEW YMF724F (DS- high performance audio controller for the PCI Bus. DS-1 consists of two separated functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine. ...
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... YMF724F Logos GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant. XG logo is a trademark of YAMAHA Corporation. SONDIUS-XG logo is a trademark that Stanford University in the United States and YAMAHA Corporation hold jointly. Sensaura logo is a trademark of Central Research Laboratories Limited. ...
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... YMF724F PIN CONFIGURATION YMF724F-V GP4 1 2 GP5 GP6 3 4 GP7 RXD 5 6 TXD ROMDO/VOLDW ROMSK/VOLUP# VDD5 9 10 VDD3 VSS 11 12 VSS IRQ5 13 14 IRQ7 IRQ9 15 16 IRQ10 IRQ11 17 18 INTA# VSS 19 20 RST# VDD5 21 22 PVSS PCICLK 23 24 PVDD GNT# ...
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... YMF724F PIN DESCRIPTION 1. PCI Bus Interface (53-pin) name I/O PCICLK I RST# I AD[31:0] IO C/BE[3:0]# IO PAR IO FRAME# IO IRDY# IO TRDY# IO STOP# IO IDSEL I DEVSEL# IO REQA# O GNTA# I PCREQ# O PCGNT# I PERR# IO SERR# O INTA# O SERIRQ AC’97 Interface (6-pin) Name I/O CRST# O CMCLK O CBCLK I CSDO O CSDI I CSYNC O Type Size P PCI Clock ...
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... YMF724F 3. YMF727(AC3F2) Interface (9-pin) name I/O XRST# O ACS# O ASCLK O ACDO O ACDI I ALRCK O ABCLK O ASDO O ASDI I 4. SPDIF Interface (1-pin) name I/O DIT O 5. Legacy Device Interface (16-pin) name I/O IRQ5 O IRQ7 O IRQ9 O IRQ10 O IRQ11 O GP[3:0] I GP[7:4] I GREF I RXD I TXD O type size C 2mA Reset for local device ...
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... YMF724F 6. Miscellaneous (15-pin) name I/O ROMCS O ROMSK / VOLUP# IO ROMDO / VOLDW# IO ROMDI / TEST2# I XI24 I XO24 O TEST[7:4,1:0]# I TEST3# IO LOOPF[1:0] - Note) Hardware volume and EEPROM interface can not be used at the same time. When both hardware volume and EEPROM are not used, do not connect these pins externally. ...
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... YMF724F BLOCK DIAGRAM PC-PCI / Legacy Audio D-DMA / S-IRQ PCI Bus BUS Master Interface DMA Controller SB Pro Rate Converter FM / Mixer MPU401 Joystick PCI Audio XG Synthesizer Direct Sound Acc. Wave In/Out Memory -7- AC'97 Interface SPDIF (output) AC3F2 Interface January 14, 1999 ...
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... YMF724F SYSTEM DIAGRAM -8- January 14, 1999 ...
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... YMF724F FUNCTION OVERVIEW 1. PCI INTERFACE DS-1 supports the PCI bus interface and complies to PCI revision 2.1. 1-1. PCI Bus Command DS-1 supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0 ...
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... YMF724F 1-2. PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2.1, DS-1 provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. ...
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... YMF724F 00 - 01h: Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.1. This register is hardwired to 1073h 03h: Device ID Read Only Default: 000Dh Access Bus Width: 8, 16, 32-bit b15 ...
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... YMF724F b8................SER: SERR# Enable This bit enables DS-1 to drive SERR#. “0”: Do not drive SERR#. “1”: Drives SERR# when DS-1 detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle 07h: Status Read / Write Clear Default: 0210h Access Bus Width: 8, 16, 32-bit ...
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... YMF724F 08h: Revision ID Read Only Default: 03h Access Bus Width: 8, 16, 32-bit Revision ID b[7:0] ..........Revision ID This register contains the revision number of DS-1. This register is hardwired to 03h. 09h: Programming Interface Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Programming Interface b[7:0] ...
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... YMF724F 0Dh: Latency Timer Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit Latency Timer b[7:0] ..........Latency Timer When DS-1 becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer. 0Eh: Header Type Read Only Default: 00h ...
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... YMF724F 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. ...
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... YMF724F 3Ch: Interrupt Line Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit Interrupt Line b[7:0] ..........Interrupt Line This register indicates the interrupt channel that INTA# is assigned to. 3Dh: Interrupt Pin Read Only Default: 01h Access Bus Width: 8, 16, 32-bit b7 b6 ...
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... YMF724F 40 - 41h: Legacy Audio Control Read / Write Default: 907Fh Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 LAD SIEN MPUIRQ b0................SBEN: Sound Blaster Enable This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits, when LAD is set to “ ...
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... YMF724F b[7:6] ..........SDMA: Sound Blaster DMA-8 Channel Select These bits select the DMA channel for the Sound Blaster Pro block. “0”: DMA ch0 “1”: DMA ch1 “2”: reserved “3”: DMA ch3 b[10:8] ........SBIRQ: Sound Blaster IRQ Channel Select These bits select the interrupt channel for the Sound Blaster Pro block. ...
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... YMF724F 42 - 43h: Extended Legacy Audio Control Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 IMOD SBVER SMOD b[1:0] ..........FMIO: FM I/O Address allocation These bits determine the base I/O address for the of the FM Synthesizer block (FMBase). FM Synthesizer block uses 4 bytes in the I/O address space. ...
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... YMF724F b[12:11] ......SMOD: SB DMA mode These bits determine the protocol to achieve the DMAC(8237) function on the PCI bus. “0”: PC/PCI “1”: reserved “2”: Distributed DMA “3” reserved b[14:13] ......SBVER: SB Version Select These bits set the version of the SB Pro DSP. The value set in these bits is returned by sending the E1h DSP command. “ ...
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... YMF724F 46-47h: Subsystem ID Write Register Read / Write Default: 000Dh Access Bus Width: 16-bit b15 b14 b13 b12 b[15:0] ........Subsystem ID Write Register This register sets the Subsystem ID that is read from 2E-2Fh (Subsystem ID register). The default value is the DS-1 Device ID, 000Dh. IHVs must change this ID to their ID in the BIOS POST routine ...
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... YMF724F b2................DPLL1: Disable PLL1 Clock Oscillation Setting this bit to “1” disables the oscillation of PLL for the PCI Audio function. “0”: Normal (default) “1”: Disable b3................PSL0: Power Save Legacy Audio Block 0 Setting this bit to “1” stops providing the clock with the Legacy Audio function block 0. This block includes FM Synthesizer and SB Pro engines. “ ...
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... YMF724F b12..............PR4: AC’97 Power down Control 4 This bit controls the power state of the AC-link in AC’97. “0”: Normal (default) “1”: Power down b13..............PR5: AC’97 Power down Control 5 Setting this bit to “1” disables the internal clock of AC’97. In case AC’97 is used with DS-1, the master clock is supplied from DS-1. Therefore, when the clock of AC’ ...
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... YMF724F 4C-4Dh: D-DMA Slave Configuration Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b0................CE: Channel Enable This bit enables the Distributed DMA function. “0”: Disable Distributed DMA “1”: Enable Distributed DMA b[2:1] ..........TS: Transfer Size These bits indicate the size of the DMA transfer. Since DS-1 supports only 8-bit DMA transfer, the bits are hardwired to 00b ...
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... YMF724F 51h: Next Item Pointer Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Next Item Pointer b[7:0] ..........Next Item Pointer DS-1 does not provide other new capability besides Power Management. This register is hardwired to 00h. 52-53h: Power Management Capabilities Read Only ...
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... YMF724F 54-55h: Power Management Control / Status Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 - - - - b[1:0] ..........PS: Power State These bits determine the power state of DS-1. DS-1 supports the following power states: “0”: D0 “1”: D1 (not supported) “2”: D2 “3”: ...
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... YMF724F 2. ISA Compatible Device DS-1 contains the following functions to maintain the compatibility with the past ISA Sound Devices. These devices are considered Legacy devices and the functions are referred to as Legacy Audio. Legacy Audio is independent from PCI Audio and can be used simultaneously. ...
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... YMF724F DS-1 supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. In addition, DS-1 supports the old type of interrupts used by ISA and the Serialized IRQ protocol. Yamaha recommends the combination of PC/PCI and Serialized IRQ. The system block diagram when using Intel chip set is shown below. ...
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... YMF724F 2-1. FM Synthesizer Block FM Synthesizer Block is register compatible with YMF289B. However, Power Management register has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase (R) FMBase (W) FMBase+1 (R/W) FMBase+2 (W) FMBase+3 (R/W) The default FMBase value is 0x0388. ...
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... YMF724F 2-1-2. FM Synthesizer Data Register FM Synthesizer Data Register Array 0 (R/W): Address D7 D6 00-01h 02h 03h 04h RST MT1 08h - NTS (*1) 20-35h AM VIB (*2) 40-55h KSL (*3) 60-75h (*4) 80-95h A0-A8h B0-B8h - - BDh DAM DVB C0-C8h *6 *6 (*5) E0-F5h - - FM Synthesizer Data Register Array 1 (R/W) Address D7 D6 00-01h 04h - - 05h ...
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... YMF724F 2-2. Sound Blaster Pro Block This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. Only playback functions are supported (record functions are not supported). However, to maintain compatibility for games designed so that every DSP command receives a correct response. ...
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... YMF724F 2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. Both SB and SB Pro commands are supported. CMD Support Function 10h o 8bit direct mode single byte digitized sound output 14h o 8bit single-cycle DMA mode digitized sound output ...
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... YMF724F 2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro. Address b7 b6 00h 04h Voice Volume L 0Ah - - 0Ch - - 0Eh - - 22h Master Volume L 26h MIDI Volume L 28h CD Volume L* 2Eh Line Volume L* F0h SBPDA - F1h F8h ...
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... YMF724F (1) Volume for MIDI 0 mute 0 0000h mute 1 0000h mute 2 0000h mute 3 0000h mute 4 0000h mute 5 0000h mute 6 0000h mute 7 0000h The default is Master = 4, MIDI = 4 (-12dB). (2) Volume for Voice 0 mute 0 0000h mute 1 0000h mute 2 0000h mute 3 0000h mute 4 0000h mute 5 0000h mute ...
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... YMF724F 2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. The internal state is made up of 218 flip flops. To read the state, these states are shifted in order and read 8 bits at a time from the SCAN DATA register. ...
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... YMF724F F1h: Scan In/ Out Data Read / Write Default: 00h SCAN DATA b[7:0] ..........SCAN DATA This is the data port for reading and writing the internal state. F8h: Interrupt Flag Register Read Only Default: 00h b0................SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. This bit is read only. Thus, read the SB DSP read port to clearing the interrupt and this bit ...
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... YMF724F 2-3. MPU401 This block is for transmitting and receiving MIDI data compatible with UART mode of “MPU401”. Full duplex operation is possible using the 16-byte FIFO for each direction, transmitting and receiving. The following shows the MPUBase I/O map for MPU401. MPUBase (R/W) MPUBase + 1h ...
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... YMF724F 3. DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block ...
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... YMF724F 3-2. D-DMA DS-1 provides the following registers to support D-DMA. D-DMA Slave Configuration Register (4C-4Dh) of the PCI Configuration register is used to set the Base address of the Slave Address. Slave Address Base + 0h Base + 0h Base + 1h Base + 1h Base + 2h Base + 2h Base + 3h Base + 3h Base + 4h Base + 4h Base + 5h Base + 5h Base + 6h Base + 6h ...
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... YMF724F 4. Interrupt Routing DS-1 supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA bus (IRQ[5,7,9,10,11]), and Serialized IRQ. The IRQs on DS-1 are routed as shown below. INTA# INTA IRQ5 IRQ7 ISA IRQ IRQ9 IRQ10 IRQ11 SERIRQ# SERIRQ PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the three protocols ...
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... YMF724F 6. Hardware Volume Control The hardware volume control determines the AC’97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used. DS-1 provides a shadow register for the AC’97 master volume. When the software accesses the AC’97 Master Volume always reflected in the shadow register ...
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... YMF724F ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Item Power Supply Voltage 1 (PVDD, VDD5) Power Supply Voltage 2 (VDD3, LVDD) Input Voltage 1 (PVDD, VDD5) Input Voltage 2 (VDD3, LVDD) Operating Ambient Temperature Storage Temperature Note : PVSS=LVSS=VSS=0[V] 2. Recommended Operating Conditions Item Power Supply Voltage 1 (PVDD, VDD5) ...
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... YMF724F 3. DC Characteristics Item High Level Input Voltage 1 Low Level Input Voltage 1 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Voltage 4 Low Level Input Voltage 4 Input Leakage Current High Level Output Voltage 1 ...
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... YMF724F 4. AC Characteristics 4-1. Master Clock (Fig.1) Item XI24 Cycle Time XI24 High Time XI24 Low Time Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0.3 V XI24 4-2. Reset (Fig.2) Item Reset Active Time after Power Stable Power Stable to Reset Rising Edge Reset Slew Rate Note : Top = 0-70° ...
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... YMF724F 4-3. PCI Interface (Fig.3, 4) Item PCICLK Cycle Time PCICLK High Time PCICLK Low Time PCICLK Slew Rate PCICLK to Signal Valid Delay Float to Active Delay Active to Float Delay Input Setup Time to PCICLK Input Hold Time for PCICLK Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0 *10: This characteristic is applicable to REQ# and PCREQ# signal ...
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... YMF724F 4-4. AC’97 / AC3F2 Master Clock Item CMCLK Cycle Time CMCLK High Time CMCLK Low Time CMCLK Rising Time CMCLK Falling Time Note : Top = 0-70°C, PVDD=5.0±0.25 V, VDD5=5.0±0.25 V, VDD3=3.3±0.3 V, LVDD=3.3±0 CMCLK Fig.5: Master Clock timing for AC’97 and AC3F2 4-5 ...
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... YMF724F CBCLK t CBIHIGH t CVAL SYNC t CVAL CSDO t CISU CSDI 4-6 AC3F2 Interface (Fig.7, 8) Item ASCLK Cycle Time ASCLK High Time ASCLK Low Time ASCLK to Signal Valid Delay Output Hold Time for ASCLK Input Setup Time to ASCLK Input Hold Time for ASCLK ABCLK Cycle Time ...
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... YMF724F ASCLK ACS, ACDO ACDI ABCLK ASDO, ALRCK ASDI t ASCCYC 0 ASCLOW ASCHIGH t ACVAL t t ACISU ACIH Fig.7: AC3F2 Control Interface timing t ABICYC 0 ABILOW ABIHIGH t ASVAL t t ASISU ASIH Fig.8: AC3F2 Audio Interface timing -48- 2 ACOH 2.2 V 0.8 V 2.2 V 0.8 V 2 ASOH 2 ...
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... YMF724F EXTERNAL DIMENSIONS YMF724F-V 109 144 LEAD THICKNESS : 0.15+0.10 The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. ...
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... YMF724F 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document ...