PIC16F630-I/ST Microchip Technology, PIC16F630-I/ST Datasheet - Page 68

• Manufacturer Part Number: PIC16F630-I/ST
• Description: IC MCU FLASH 1KX14 EEPROM14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F630-I/ST

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Controller Family/series: PIC16F
• No. Of I/o's: 12
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 1 x 8
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16F630/676
TABLE 9-8:
9.5
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W register and
STATUS register). This must be implemented in
software.
Example 9-2 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined
at 0x20 in Bank 0 and it must also be defined at 0xA0
in Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 9-2:
• Stores the W register
• Stores the STATUS register in Bank 0
• Executes the ISR code
• Restores the Status (and bank select bit register)
• Restores the W register
EXAMPLE 9-2:
DS40039F-page 68
0Bh, 8Bh INTCON
0Ch
8Ch
Legend: x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
MOVWF
SWAPF
BCF
MOVWF
SWAPF
MOVWF
SWAPF
SWAPF
Address
:
:(ISR)
:
W_TEMP
STATUS,W
STATUS,RP0
STATUS_TEMP
STATUS_TEMP,W;swap STATUS_TEMP register into
STATUS
W_TEMP,F
W_TEMP,W
Context Saving During Interrupts
Shaded cells are not used by the Interrupt module.
PIR1
PIE1
Name
SUMMARY OF INTERRUPT REGISTERS
;copy W to temp register,
;swap status to be saved into W
;change to bank 0 regardless of
;save status to bank 0 register
;move W into STATUS register
;swap W_TEMP
;swap W_TEMP into W
Bit 7
EEIF
EEIE
GIE
SAVING THE STATUS AND
W REGISTERS IN RAM
could be in either bank
current bank
W, sets bank to original state
PEIE
ADIF
ADIE
Bit 6
Bit 5
T0IE
—
—
INTE
Bit 4
—
—
CMIF
CMIE
RAIE
Bit 3
9.6
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin. That means that the WDT will run,
even if the clock on the OSC1 and OSC2 pins of the
device has been stopped (for example, by execution of
a
time-out generates a device Reset. If the device is in
Sleep mode, a WDT time-out causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the Con-
figuration bit WDTE as clear (Section 9.1 “Configura-
tion Bits”).
9.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). The time-out periods vary with tempera-
ture, V
DC specs). If longer time-out periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, time-out periods up to
2.3 seconds can be realized.
The
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time-out.
9.6.2
It should also be taken in account that under worst-
case conditions (i.e., V
Max. WDT prescaler) it may take several seconds
before a WDT time-out occurs.
SLEEP
Bit 2
T0IF
CLRWDT
—
—
DD
Watchdog Timer (WDT)
instruction). During normal operation, a WDT
and process variations from part to part (see
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
INTF
Bit 1
—
—
and
SLEEP
TMR1IF 00-- 0--0 00-- 0--0
TMR1IE 00-- 0--0 00-- 0--0
RAIF
Bit 0
DD
 2010 Microchip Technology Inc.
= Min., Temperature = Max.,
instructions clear the WDT
0000 0000 0000 000u
POR, BOD
Value on
Value on all
Resets
other