AT89S52-24AU Atmel, AT89S52-24AU Datasheet - Page 33

• Manufacturer Part Number: AT89S52-24AU
• Description: IC MCU 8K FLASH 24MHZ 44-TQFP
• Manufacturer: Atmel
• Series: 89Sr

Specifications of AT89S52-24AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Package: 44TQFP
• Device Core: 8051
• Family Name: 89S
• Maximum Speed: 24 MHz
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 32
• Interface Type: UART
• Number Of Timers: 3
• Processor Series: AT89x
• Core: 8051
• Data Ram Size: 256 B
• Maximum Clock Frequency: 24 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Minimum Operating Temperature: - 40 C
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 3
• Digital Ic Case Style: TQFP
• Supply Voltage Range: 4V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

34. Serial Port Timing: Shift Register Mode Test Conditions
The values in this table are valid for V
35. Shift Register Mode Timing Waveforms
36. AC Testing Input/Output Waveforms
Note:
37. Float Waveforms
Note:
1919D–MICRO–6/08
Symbol
t
t
t
t
t
XLXL
QVXH
XHQX
XHDX
XHDV
1. AC Inputs during testing are driven at V
1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
INSTRUCTION
for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V
float when a 100 mV change from the loaded V
WRITE TO SBUF
OUTPUT DATA
INPUT DATA
CLEAR RI
Parameter
Serial Port Clock Cycle Time
Output Data Setup to Clock Rising Edge
Output Data Hold After Clock Rising Edge
Input Data Hold After Clock Rising Edge
Clock Rising Edge to Input Data Valid
CLOCK
ALE
(1)
0
t
V
QVXH
V
LOAD
CC
CC
- 0.5V
= 4.0V to 5.5V and Load Capacitance = 80 pF.
0.45V
t
1
XHDV
V
V
0
LOAD
LOAD
VALID
CC
+ 0.1V
- 0.1V
- 0.5V
2
t
XLXL
t
1
OH
XHQX
VALID
/V
Timing Reference
OL
0.2 V
0.2 V
(1)
TEST POINTS
3
level occurs.
Points
t
Min
700
XHDX
2
1.0
50
VALID
CC
CC
12 MHz Osc
0
+ 0.9V
- 0.1V
4
3
VALID
Max
700
V
V
OL
OL
5
IH
- 0.1V
+ 0.1V
min. for a logic 1 and V
4
VALID
10 t
2 t
12 t
CLCL
CLCL
6
Min
Variable Oscillator
0
CLCL
5
VALID
-133
-80
7
6
VALID
10 t
IL
SET TI
SET RI
CLCL
max. for a logic 0.
Max
8
7
AT89S52
-133
VALID
Units
μs
ns
ns
ns
ns
33