PIC16F627A-I/SO Microchip Technology, PIC16F627A-I/SO Datasheet

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... Microcontrollers with nanoWatt Technology  2004 Microchip Technology Inc. PIC16F627A/628A/648A Flash-Based 8-Bit CMOS Preliminary Data Sheet DS40044B ...

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... ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. ...

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... Flash (words) PIC16F627A 1024 PIC16F628A 2048 PIC16F648A 4096  2004 Microchip Technology Inc. PIC16F627A/628A/648A Low Power Features: • Standby Current: - 100 nA @ 2.0V, typical • Operating Current kHz, 2.0V, typical - 120 MHz, 2.0V, typical • Watchdog Timer Current - 2.0V, typical • Timer1 oscillator current kHz, 2.0V, typical • ...

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... RA2/AN2/V REF RA3/AN3/CMP1 2 RA4/TOCKI/CMP2 3 4 RA5/MCLR RB0/INT 6 RB1/RX/ RB2/TX/CK RB3/CCP1 9 SSOP PIC16F627A/628A/648A DS40044B-page 2 18 RA1/AN1 17 RA0/AN0 16 RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RB7/T1OSI/PGD 13 12 RB6/T1OSO/T1CKI/PGC RB5 11 10 RB4/PGM 28-Pin QFN RA5/MCLR PIC16F627A/628A NC 4 PIC16F648A RB0/INT 7 Preliminary 21 RA7/OSC1/CLKIN 20 RA6/OSC2/CLKOUT RB7/T1OSI/PGD 15 RB6/T1OSO/T1CKI/PGC  2004 Microchip Technology Inc. ...

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... Table of Contents 1.0 General Description...................................................................................................................................................................... 5 2.0 PIC16F627A/628A/648A Device Varieties ................................................................................................................................... 7 3.0 Architectural Overview ................................................................................................................................................................. 9 4.0 Memory Organization ................................................................................................................................................................. 15 5.0 I/O Ports ..................................................................................................................................................................................... 31 6.0 Timer0 Module ........................................................................................................................................................................... 45 7.0 Timer1 Module ........................................................................................................................................................................... 48 8.0 Timer2 Module ........................................................................................................................................................................... 52 9.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 55 10.0 Comparator Module.................................................................................................................................................................... 61 11.0 Voltage Reference Module......................................................................................................................................................... 67 12.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Module........................................................................ 69 13 ...

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... PIC16F627A/628A/648A NOTES: DS40044B-page 4 Preliminary  2004 Microchip Technology Inc. ...

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... QFN All PICmicro® Family devices have Power-on Reset, selectable Watchdog Timer, selectable Code Protect and high I/O current capability. All PIC16F627A/628A/648A Family devices use serial programming with clock pin RB6 and data pin RB7.  2004 Microchip Technology Inc. ...

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... PIC16F627A/628A/648A NOTES: DS40044B-page 6 Preliminary  2004 Microchip Technology Inc. ...

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... A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC16F627A/628A/648A Product Identification System, at the end of this data sheet. When placing orders, please use this page of the data sheet to specify the correct part number. ...

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... PIC16F627A/628A/648A NOTES: DS40044B-page 8 Preliminary  2004 Microchip Technology Inc. ...

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... PIC16LF648A 4096 x 14 256 x 8 The PIC16F627A/628A/648A can directly or indirectly address its register files or data memory. All Special Function Registers (SFR), including the program counter, are mapped in the data memory. The PIC16F627A/628A/648A have an orthogonal (symmet- rical) instruction set that makes it possible to carry out any operation, on any register, using any Addressing mode. This symmetrical nature and lack of ‘ ...

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... PIC16F627A/628A/648A FIGURE 3-1: BLOCK DIAGRAM 13 Program Counter Flash Program Memory Program 14 Bus Instruction reg Direct Addr 8 Instruction Start-up Timer Decode & Control Timing Generation OSC1/CLKIN OSC2/CLKOUT Programming MCLR Timer0 Comparator V CCP1 REF Note: Higher order bits are from the Status Register. ...

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... TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION Name Function RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/V RA2 REF AN2 V REF RA3/AN3/CMP1 RA3 AN3 CMP1 RA4/T0CKI/CMP2 RA4 T0CKI CMP2 RA5/MCLR/V RA5 PP MCLR V PP RA6/OSC2/CLKOUT RA6 OSC2 CLKOUT RA7/OSC1/CLKIN RA7 OSC1 CLKIN RB0/INT RB0 INT ...

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... PIC16F627A/628A/648A TABLE 3-2: PIC16F627A/628A/648A PINOUT DESCRIPTION Name Function RB4/PGM RB4 PGM RB5 RB5 RB6/T1OSO/T1CKI/PGC RB6 T1OSO T1CKI PGC RB7/T1OSI/PGD RB7 T1OSI PGD Legend Output — = Not used TTL = TTL Input DS40044B-page 12 Input Type Output Type TTL CMOS Bidirectional I/O port. Interrupt-on-pin change. ...

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... All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 3.2 Instruction Flow/Pipelining An instruction cycle consists of four Q cycles (Q1, Q2, Q3 and Q4) ...

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... PIC16F627A/628A/648A NOTES: DS40044B-page 14 Preliminary  2004 Microchip Technology Inc. ...

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... The PIC16F627A/628A/648A has a 13-bit program counter capable of addressing program memory space. Only the first (0000h - 03FFh) for the PIC16F627A (0000h - 07FFh) for the PIC16F628A and (0000h - 0FFFh) for the PIC16F648A are physically implemented. Accessing a location above these boundaries will cause a wrap- ...

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... PIC16F627A/628A/648A FIGURE 4-2: DATA MEMORY MAP OF THE PIC16F627A AND PIC16F628A (1) Indirect addr. Indirect addr. 00h 01h TMR0 02h PCL STATUS 03h FSR 04h 05h PORTA PORTB 06h 07h 08h 09h PCLATH 0Ah INTCON 0Bh 0Ch PIR1 0Dh TMR1L 0Eh TMR1H 0Fh ...

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... CMCON 20h General Purpose Register 80 Bytes 6Fh 70h 16 Bytes 7Fh Bank 0 Unimplemented data memory locations, read as ‘0’. Note 1: Not a physical register.  2004 Microchip Technology Inc. PIC16F627A/628A/648A (1) (1) Indirect addr. 80h TMR0 OPTION 81h PCL PCL 82h STATUS STATUS 83h ...

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... PIC16F627A/628A/648A 4.2.2 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and Periph- eral functions for controlling the desired operation of the device (Table 4-3). These registers are static RAM. The special registers can be classified into two sets (core and peripheral). The SFRs associated with the “ ...

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... VROE Legend: — = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unim- plemented Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...

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... PIC16F627A/628A/648A TABLE 4-5: SPECIAL FUNCTION REGISTERS SUMMARY BANK2 Address Name Bit 7 Bit 6 Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx Timer0 module’s Register 101h TMR0 102h PCL Program Counter's (PC) Least Significant Byte ...

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... Unimplemented Legend: — = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-6 and Table 14-7.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 T0CS T0SE ...

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... PIC16F627A/628A/648A 4.2.2.1 Status Register The Status Register, shown in Register 4-1, contains the arithmetic status of the ALU; the Reset status and the bank select bits for data memory (SRAM). The Status Register can be the destination for any instruction, like any other register. If the Status Register ...

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... Legend Readable bit -n = Value at POR  2004 Microchip Technology Inc. PIC16F627A/628A/648A Note: To achieve a 1:1 prescaler assignment for TMR0, assign the prescaler to the WDT (PSA = 1). See Section 6.3.1 "Switching Prescaler Assignment". R/W-1 R/W-1 R/W-1 T0CS T0SE ...

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... PIC16F627A/628A/648A 4.2.2.3 INTCON Register The INTCON register is a readable and writable register, which contains the various enable and flag bits for all interrupt sources except the comparator module. See Section 4.2.2.4 "PIE1 Register" Section 4.2.2.5 "PIR1 Register" for a description of the comparator enable and flag bits. ...

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... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit -n = Value at POR  2004 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 U-0 RCIE TXIE — CCP1IE W = Writable bit U = Unimplemented bit, read as ‘ ...

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... PIC16F627A/628A/648A 4.2.2.5 PIR1 Register This register contains interrupt flag bits. REGISTER 4-5: PIR1 REGISTER (ADDRESS: 0Ch) R/W-0 R/W-0 EEIF CMIF bit 7 bit 7 EEIF: EEPROM Write Operation Interrupt Flag bit 1 = The write operation completed (must be cleared in software The write operation has not completed or has not been started ...

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... No Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend Readable bit -n = Value at POR  2004 Microchip Technology Inc. PIC16F627A/628A/648A Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent Resets to see if BOR is cleared, occurred. The BOR Status bit is a “ ...

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... Refer to the application note “Implementing a Table Read” (AN556). 4.3.2 STACK The PIC16F627A/628A/648A family has an 8-level deep x 13-bit wide hardware stack (Figure 4-1). The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch ...

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... FIGURE 4-5: DIRECT/INDIRECT ADDRESSING PIC16F627A/628A/648A Status Direct Addressing Register from opcode RP1 RP0 6 bank select location select 00h RAM File Registers 7Fh Bank 0 Note: For memory map detail see Figure 4-3, Figure 4-2 and Figure 4-1.  2004 Microchip Technology Inc. ...

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... PIC16F627A/628A/648A NOTES: DS40044B-page 30 Preliminary  2004 Microchip Technology Inc. ...

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... I/O PORTS The PIC16F627A/628A/648A have two ports, PORTA and PORTB. Some pins for these I/O ports are multiplexed with alternate functions for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. ...

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... PIC16F627A/628A/648A FIGURE 5-2: BLOCK DIAGRAM OF RA2/V PIN REF Data Bus PORTA CK Q Data Latch TRISA Analog CK Q Input Mode TRIS Latch (CMCON Reg.) RD Schmitt Trigger TRISA Input Buffer PORTA To Comparator V ROE V REF FIGURE 5-3: BLOCK DIAGRAM OF THE RA3/AN3 PIN Data Bus ...

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... MCLRE MCLR circuit MCLR Filter Schmitt Trigger Program Input Buffer mode HV Detect Data Bus RD V TRISA PORTA  2004 Microchip Technology Inc. PIC16F627A/628A/648A Comparator Mode = 110 (CMCON Reg FIGURE 5-6: PIN PP From OSC1 CLKOUT(F OSC D WR PORTA OSC Data Latch (2) 101, 111) ...

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... PIC16F627A/628A/648A FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKIN PIN To Clock Circuits Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA ( 100, 101 OSC RD PORTA Note 1: INTOSC with CLKOUT, and INTOSC with I/O. DS40044B-page Schmitt Trigger Input Buffer EN Preliminary V DD RA7/OSC1/CLKIN Pin ...

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... PP RA6/OSC2/CLKOUT RA6 OSC2 CLKOUT RA7/OSC1/CLKIN RA7 OSC1 XTAL CLKIN Legend Output — = Not used TTL = TTL Input  2004 Microchip Technology Inc. PIC16F627A/628A/648A Output Type Type ST CMOS Bidirectional I/O port AN — Analog comparator input ST CMOS Bidirectional I/O port AN — Analog comparator input ...

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... PIC16F627A/628A/648A TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Address Name Bit 7 Bit 6 05h PORTA RA7 RA6 85h TRISA TRISA7 TRISA6 1Fh CMCON C2OUT C1OUT 9Fh VRCON VREN VROE Legend: — = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: Shaded bits are not used by PORTA ...

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... Q Data Latch TRISB CK Q TRIS Latch TTL RD TRISB Input Buffer PORTB INT Schmitt Trigger  2004 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 5- RBPU Weak Pull-up P SPEN V DD USART Data Output Data Bus RB0/INT WR PORTB TRISB (1) Peripheral OE RD TRISB RD PORTB USART Receive Input ...

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... PIC16F627A/628A/648A FIGURE 5-10: BLOCK DIAGRAM OF RB2/TX/CK PIN RBPU SPEN USART TX/CK Output 1 Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch (1) Peripheral OE RD TRISB PORTB USART Slave Clock In Schmitt Trigger Note 1: Peripheral OE (output enable) is only active if peripheral select is active. DS40044B-page 38 ...

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... WR TRISB CK TRIS Latch RD TRISB LVP (Configuration Bit) RD PORTB PGM input Set RBIF From other RB<7:4> pins Note: The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Schmitt Trigger Q Q Preliminary weak pull-up ...

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... PIC16F627A/628A/648A FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN RBPU Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch RD TRISB RD PORTB Set RBIF From other RB<7:4> pins DS40044B-page 40 TTL input buffer Preliminary  2004 Microchip Technology Inc weak P pull-up RB5 pin V SS ...

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... FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN RBPU Data Bus WR PORTB WR TRISB TRIS Latch RD TRISB T1OSCEN RD PORTB TMR1 Clock From RB7 Serial programming clock Set RBIF  2004 Microchip Technology Inc. PIC16F627A/628A/648A Data Latch Schmitt Trigger From other RB<7:4> pins Preliminary V DD ...

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... PIC16F627A/628A/648A FIGURE 5-15: BLOCK DIAGRAM OF THE RB7/T1OSI PIN RBPU To RB6 Data Bus WR PORTB WR TRISB RD TRISB T10SCEN RD PORTB Serial programming input Set RBIF DS40044B-page Data Latch TRIS Latch Q Q From other RB<7:4> pins EN Preliminary V DD weak pull-up P TMR1 oscillator V DD RB7/T1OSI pin ...

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... OPTION RBPU INTEDG Legend unchanged unknown Note 1: Shaded bits are not used by PORTB. 2: LVP Configuration Bit sets RB4 functionality.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Output Type TTL CMOS Bidirectional I/O port. Can be software programmed for internal weak pull-up. ST — ...

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... PIC16F627A/628A/648A 5.3 I/O Programming Considerations 5.3.1 BIDIRECTIONAL I/O PORTS Any instruction that writes, operates internally as a read followed by a write operation. The BCF and BSF instruc- tions, for example, read the register into the CPU, execute the bit operation and write the result back to the register ...

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... The Timer0 interrupt cannot wake the processor from Sleep since the timer is shut off during Sleep.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 6.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (T synchronization ...

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... PIC16F627A/628A/648A 6.3 Timer0 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module postscaler for the Watchdog Timer. A prescaler assignment for the Timer0 module means that there is no postscaler for the Watchdog Timer, and vice-versa. FIGURE 6-1: BLOCK DIAGRAM OF THE TIMER0/WDT ...

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... Unimplemented locations, read as ‘0’ unchanged unknown Note 1: Shaded bits are not used by Timer0 module. 2: Option is referred by OPTION_REG in MPLAB  2004 Microchip Technology Inc. PIC16F627A/628A/648A To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. ...

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... Timer1 also has an internal “Reset input”. This Reset can be generated by the CCP module (Section 9.0 "Capture/Compare/PWM Register 7-1 shows the Timer1 control register. For the PIC16F627A/628A/648A, when the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/T1OSI and RB6/T1OSO/T1CKI pins become inputs. That is, the TRISB<7:6> value is ignored. ...

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... T1OSC RB6/T1OSO/T1CKI RB7/T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 7.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE When an external clock input is used for Timer1 in synchronized Counter mode, it must meet certain requirements ...

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... PIC16F627A/628A/648A 7.3 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor ...

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... T1CKPS1 Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer1 module.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 7.5 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will Reset Timer1 ...

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... PIC16F627A/628A/648A 8.0 TIMER2 MODULE Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device Reset. The input clock (F /4) has a prescale option of 1:1, ...

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... PR2 Timer2 Period Register Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by the Timer2 module.  2004 Microchip Technology Inc. PIC16F627A/628A/648A R/W-0 R/W-0 R/W-0 TOUTPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...

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... PIC16F627A/628A/648A NOTES: DS40044B-page 54 Preliminary  2004 Microchip Technology Inc. ...

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... Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 11xx = PWM mode Legend Readable bit -n = Value at POR  2004 Microchip Technology Inc. PIC16F627A/628A/648A TABLE 9-1: CCP Mode Capture Compare PWM (CCPR1) is ...

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... PIC16F627A/628A/648A 9.1 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RB3/CCP1. An event is defined as: • Every falling edge • Every rising edge • Every 4th rising edge • Every 16th rising edge An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON< ...

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... CCP1X Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by Capture and Timer1.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 9.2.3 SOFTWARE INTERRUPT MODE When generate software interrupt is chosen the CCP1 pin is not affected. Only a CCP interrupt is generated (if enabled) ...

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... PIC16F627A/628A/648A 9.3 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB<3> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level ...

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... CCP1CON — — Legend unknown unchanged unimplemented read as ‘0’. Shaded cells are not used by PWM and Timer2.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Maximum PWM resolution (bits) for a given PWM frequency: PWM Resolution Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared ...

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... PIC16F627A/628A/648A NOTES: DS40044B-page 60 Preliminary  2004 Microchip Technology Inc. ...

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... Figure 10-1 shows the Comparator modes and CM2:CM0 bit settings Legend Readable bit -n = Value at POR  2004 Microchip Technology Inc. PIC16F627A/628A/648A The CMCON register, shown in Register 10-1, controls the comparator input and output multiplexers. A block two analog diagram of the comparator is shown in Figure 10-1. ...

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... PIC16F627A/628A/648A 10.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select the mode. Figure 10-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode. FIGURE 10-1: ...

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... An external or internal reference signal may be used depending on the comparator Operating mode. The analog signal that is present compared to the IN signal and the digital output of the comparator IN is adjusted accordingly (Figure 10-2).  2004 Microchip Technology Inc. PIC16F627A/628A/648A FIGURE 10-2: Vin+ Vin Result 10 ...

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... PIC16F627A/628A/648A 10.5 Comparator Outputs The comparator outputs are read through the CMCON register. These bits are read only. The comparator outputs may also be directly output to the RA3 and RA4 I/O pins. When the CM<2:0> = 110 or 001, multiplexors in the output path of the RA3 and RA4/T0CK1 pins will switch and the output of each pin will be the unsynchro- nized output of the comparator ...

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... Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition and allow flag bit CMIF to be cleared.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 10.7 Comparator Operation During Sleep When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled ...

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... PIC16F627A/628A/648A FIGURE 10-4: ANALOG INPUT MODE R < PIN Legend C PIN LEAKAGE TABLE 10-1: REGISTERS ASSOCIATED WITH COMPARATOR MODULE Address Name Bit 7 Bit 6 1Fh CMCON C2OUT C1OUT 0Bh, 8Bh, INTCON GIE PEIE 10Bh, 18Bh 0Ch PIR1 EEIF CMIF 8Ch PIE1 EEIE CMIE ...

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... FIGURE 11-1: VOLTAGE REFERENCE BLOCK DIAGRAM REN 8R V REF Note defined in Table 17-3.  2004 Microchip Technology Inc. PIC16F627A/628A/648A The equations used to calculate the output of the Voltage Reference are as follows REF The setting time of the Voltage Reference must be considered when changing the V (Table 17-3) ...

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... PIC16F627A/628A/648A EXAMPLE 11-1: VOLTAGE REFERENCE CONFIGURATION MOVLW 0x02 ;4 Inputs Muxed MOVWF CMCON ;to 2 comps. BSF STATUS,RP0 ;go to Bank 1 MOVLW 0x07 ;RA3-RA0 are MOVWF TRISA ;outputs MOVLW 0xA6 ;enable V REF MOVWF VRCON ;low range set V BCF STATUS,RP0 ;go to Bank 0 CALL DELAY10 ;10 s delay 11 ...

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... SREN/CREN overrides TXEN in SYNC mode. Legend Readable bit -n = Value at POR  2004 Microchip Technology Inc. PIC16F627A/628A/648A The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous - Master (half-duplex) • Synchronous - Slave (half-duplex) Bit SPEN (RCSTA<7>), and bits TRISB<2:1>, have to ...

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... PIC16F627A/628A/648A REGISTER 12-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS: 18h) R/W-0 R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit (Configures RB1/RX/DT and RB2/TX/CK pins as serial port pins when bits TRISB<2:1> are set Serial port enabled 0 = Serial port disabled bit 6 ...

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... RCSTA SPEN RX9 99h SPBRG Legend unknown unimplemented read as ‘0’. Shaded cells are not used by the BRG.  2004 Microchip Technology Inc. PIC16F627A/628A/648A EXAMPLE 12-1: Desired Baud Rate , the nearest Calculated Baud Rate (Calculated Baud Rate - Desired Baud Rate) --------------------------------------------------------------------------------------------------------- - Error ...

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... PIC16F627A/628A/648A TABLE 12-3: BAUD RATES FOR SYNCHRONOUS MODE MHz SPBRG OSC BAUD RATE (K) KBAUD ERROR (decimal) 0.3 NA — 1.2 NA — 2.4 NA — 9.6 NA — 19.2 19.53 +1.73% 76.8 76.92 +0.16% 96 96.15 +0.16% 300 294.1 -1.96 500 500 0 HIGH 5000 — LOW 19.53 — ...

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... NA — — 300 NA — 500 NA — HIGH 55.93 — LOW 0.2185 —  2004 Microchip Technology Inc. PIC16F627A/628A/648A 16 MHz SPBRG value value KBAUD ERROR (decimal) — NA — — 255 1.202 +0.16% 207 129 2.404 +0.16% 103 32 9.615 +0 ...

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... PIC16F627A/628A/648A TABLE 12-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = MHz SPBRG OSC BAUD RATE (K) KBAUD ERROR (decimal) 9600 9.615 +0.16% 19200 19.230 +0.16% 38400 37.878 -1.36% 57600 56.818 -1.36% 115200 113.636 -1.36% 250000 250 0 625000 625 0 1250000 1250 7.16 MHz SPBRG ...

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... Baud CLK x4 CLK Q2, Q4 CLK FIGURE 12-3: RX PIN SAMPLING SCHEME, BRGH = 1 RX pin Baud CLK First falling edge after RX pin goes low x4 CLK Q2, Q4 CLK  2004 Microchip Technology Inc. PIC16F627A/628A/648A Start bit Baud CLK for all but Start bit Samples ...

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... PIC16F627A/628A/648A FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 RX (RB1/RX/DT pin) Baud CLK x16 CLK 12.2 USART Asynchronous Mode In this mode, the USART uses standard non-return-to- zero (NRZ) format (one Start bit, eight or nine data bits and one Stop bit). The most common data format is 8-bit ...

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... RB2/TX/CK (pin) Start Bit TXIF bit (Transmit buffer reg. empty flag) WORD 1 TRMT bit Transmit Shift Reg (Transmit shift reg. empty flag)  2004 Microchip Technology Inc. PIC16F627A/628A/648A Data Bus TXREG register 8 MSb LSb (8) 0 ² ² ² TSR register TRMT ...

Page 80

... PIC16F627A/628A/648A FIGURE 12-7: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 2 Word 1 BRG output (shift clock) RB2/TX/CK (pin) Start Bit TXIF bit (interrupt reg. flag) TRMT bit WORD 1 (Transmit shift Transmit Shift Reg. reg. empty flag) Note: This timing diagram shows two consecutive transmissions. ...

Page 81

... ADEN RX9 ADEN RSR<8>  2004 Microchip Technology Inc. PIC16F627A/628A/648A double buffered register, (i.e two deep FIFO possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte begin shifting to the RSR register. On the detection of the Stop bit of the third byte, if the RCREG register is still full then overrun error bit OERR (RCSTA< ...

Page 82

... PIC16F627A/628A/648A FIGURE 12-9: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT START RB1/RX/DT (PIN) BIT BIT0 BIT1 RCV SHIFT REG RCV BUFFER REG BIT8 = 0, DATA BYTE READ RCV BUFFER REG RCREG RCIF (INTERRUPT FLAG) ‘1’ ADEN = 1 (ADDRESS MATCH ENABLE) Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADEN = 1 and Bit ...

Page 83

... CMIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as ‘0’. Shaded cells are not used for Asynchronous Reception.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 ...

Page 84

... PIC16F627A/628A/648A 12.3 USART Address Detect Function 12.3.1 USART 9-BIT RECEIVER WITH ADDRESS DETECT When the RX9 bit is set in the RCSTA register, 9 bits are received and the ninth bit is placed in the RX9D bit of the RCSTA register. The USART module has a special provision for multi-processor communication. ...

Page 85

... TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Clearing enable bit TXEN, during a transmission, will cause the transmission to be aborted and will Reset the transmitter. The DT and CK pins will revert to hi-imped- ance ...

Page 86

... PIC16F627A/628A/648A TABLE 12-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Address Name Bit 7 Bit 6 0Ch PIR1 EEIF CMIF RCIF 18h RCSTA SPEN RX9 SREN CREN 19h TXREG USART Transmit data register 8Ch PIE1 EEIE CMIE RCIE 98h TXSTA CSRC TX9 TXEN SYNC ...

Page 87

... SPBRG Baud Rate Generator Register Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Synchronous Master Reception.  2004 Microchip Technology Inc. PIC16F627A/628A/648A with a new value, therefore it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information ...

Page 88

... PIC16F627A/628A/648A FIGURE 12-14: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1Q2Q3 Q4Q1Q2Q3Q4Q1Q2Q3Q4Q1Q2Q3Q4 BIT0 BIT1 RB1/RX/DT PIN RB2/TX/CK PIN WRITE TO BIT SREN SREN BIT ‘0’ CREN BIT RCIF BIT (INTERRUPT) READ RXREG Note: Timing diagram demonstrates Sync Master Mode with bit SREN = ‘1’ and bit BRG = ‘0’. ...

Page 89

... SPBRG Baud Rate Generator Register Legend unknown unimplemented read as ‘0’. Shaded cells are not used for Synchronous Slave Reception.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 2. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC ...

Page 90

... PIC16F627A/628A/648A NOTES: DS40044B-page 88 Preliminary  2004 Microchip Technology Inc. ...

Page 91

... EEADR REGISTER (ADDRESS: 9Bh) R/W-x R/W-x EADR7 EADR6 bit 7 bit 7 PIC16F627A/628A - Unimplemented Address: Must be set to ‘0’ PIC16F648A - EEADR: Set to ‘1’ specifies top 128 locations (128-256) of EEPROM Read/Write Operation bit 6-0 EEADR: Specifies one of 128 locations of EEPROM Read/Write Operation Legend Readable bit -n = Value at POR  ...

Page 92

... The PIC16F648A EEADR register addresses 256 bytes of data EEPROM. All eight bits in the register (EEADR<7:0>) are required. The PIC16F627A/628A EEADR register addresses only the first 128 bytes of data EEPROM so only seven of the eight bits in the register (EEADR<6:0>) are required. The upper bit is address decoded. This means that this bit should always be '0' to ensure that the address is in the 128 byte memory space ...

Page 93

... WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set.  2004 Microchip Technology Inc. PIC16F627A/628A/648A At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set. The user can either enable this interrupt or poll this bit ...

Page 94

... PIC16F627A/628A/648A 13.7 Using the Data EEPROM The data EEPROM is a high endurance, byte address- able array that has been optimized for the storage of frequently changing information variables or other data that are updated often). Frequently changing values will typically be updated more often than specification D124. If this is not the case, an array refresh must be performed ...

Page 95

... Sleep 10. Code protection 11. ID Locations 12. In-Circuit Serial Programming™ (ICSP™) The PIC16F627A/628A/648A has a Watchdog Timer which is controlled by configuration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable ...

Page 96

... CP: Flash Program Memory Code Protection bit (PIC16F648A Code protection off 0 = 0000h to 0FFFh code protected (PIC16F628A Code protection off 0 = 0000h to 07FFh code protected (PIC16F627A Code protection off 0 = 0000h to 03FFh code protected bit 12-9: Unimplemented: Read as ‘0’ (3) bit 8: CPD: Data Code Protection bit ...

Page 97

... Oscillator Configurations 14.2.1 OSCILLATOR TYPES The PIC16F627A/628A/648A can be operated in eight different oscillator options. The user can program three configuration bits (FOSC2 through FOSC0) to select one of these eight modes: • LP Low Power Crystal • XT Crystal/Resonator • HS High Speed Crystal/Resonator • RC External Resistor/Capacitor (2 modes) • ...

Page 98

... EXTERNAL CLOCK IN For applications where a clock is already available elsewhere, users may directly drive the PIC16F627A/ 628A/648A provided that this external clock source meets the AC/DC timing requirements listed in Section 17.6 "Timing Diagrams and Specifica- tions" ...

Page 99

... SPECIAL FEATURE: DUAL SPEED OSCILLATOR MODES A software programmable dual speed Oscillator mode is provided when the PIC16F627A/628A/648A is configured in the INTOSC Oscillator mode. This feature allows users to dynamically toggle the oscillator speed between 4 MHz and 37 kHz nominal in the INTOSC mode. Applications that require low current power savings, but cannot tolerate putting the part into Sleep, may use this mode ...

Page 100

... The OST time out is invoked only for XT, LP and modes and only on Power-on Reset or wake-up from Sleep. See Table 17-7. 14.4.4 BROWN-OUT RESET (BOR) The PIC16F627A/628A/648A have on-chip BOR parameters circuitry. A configuration bit, BOREN, can disable (if clear/programmed) or enable (if set) the BOR Reset circuitry falls below V DD the brown-out situation will Reset the chip ...

Page 101

... Then bringing MCLR high will begin execution immediately (see Figure 14-9). This is useful for testing purposes or to synchronize more than one PIC16F627A/628A/ 648A device operating in parallel. Table 14-6 shows the Reset conditions for some special registers, while Table 14-7 shows the Reset conditions for all the registers ...

Page 102

... PIC16F627A/628A/648A TABLE 14-5: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT RESET Address Name Bit 7 Bit 6 03h, 83h, STATUS IRP RP1 103h, 183h 8Eh PCON — — Legend unknown unchanged unimplemented read as ‘0’ value depends upon condition. Shaded cells are not used by Brown-out Reset. ...

Page 103

... Brown-out Reset (BOR Peripherals generating interrupts for wake-up from Sleep will change the resulting bits in the associated registers.  2004 Microchip Technology Inc. PIC16F627A/628A/648A • MCLR Reset during normal • Wake-up from Sleep operation • MCLR Reset during Sleep • ...

Page 104

... PIC16F627A/628A/648A FIGURE 14-8: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET FIGURE 14-9: TIME OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME OUT OST TIME OUT INTERNAL RESET ...

Page 105

... Transistor Q1 turns off when Internal Brown-out Reset should be dis- Vdd x abled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. DD Preliminary EXTERNAL BROWN-OUT PROTECTION CIRCUIT MCLR 40k PIC16F627A/628A/648A is below a certain level such that 0 0 DS40044B-page 103 ...

Page 106

... PIC16F627A/628A/648A 14.5 Interrupts The PIC16F627A/628A/648A has 10 sources of interrupt: • External Interrupt RB0/INT • TMR0 Overflow Interrupt • PORTB Change Interrupts (pins RB7:RB4) • Comparator Interrupt • USART Interrupt TX • USART Interrupt RX • CCP Interrupt • TMR1 Overflow Interrupt • TMR2 Match Interrupt • ...

Page 107

... CLKOUT is available in RC and INTOSC Oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 14.5.3 PORTB INTERRUPT An input change on PORTB <7:4> sets the RBIF (INTCON<0>) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON< ...

Page 108

... PIC16F627A/628A/648A TABLE 14-8: SUMMARY OF INTERRUPT REGISTERS Address Name Bit 7 Bit 6 0Bh, 8Bh, INTCON GIE PEIE 10Bh, 18Bh 0Ch PIR1 EEIF CMIF 8Ch PIE1 EEIE CMIE Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Reset and Watchdog Timer Reset during normal operation ...

Page 109

... PD bit in the Status Register is cleared, the TO bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had, before SLEEP was executed (driving high, low, or hi-impedance).  2004 Microchip Technology Inc. PIC16F627A/628A/648A 0 M WDT POSTSCALER/ U TMR0 PRESCALER X 1 ...

Page 110

... PIC16F627A/628A/648A 14.8.1 WAKE-UP FROM SLEEP The device can wake-up from Sleep through one of the following events: 1. External Reset input on MCLR pin 2. Watchdog Timer wake-up (if WDT was enabled) 3. Interrupt from RB0/INT pin, RB Port change, or any Peripheral Interrupt. The first event will cause a device Reset. The two latter events are considered a continuation of program execution ...

Page 111

... In-Circuit Serial Programming The PIC16F627A/628A/648A microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manu- facture boards with unprogrammed devices and then program the microcontroller just before shipping the product ...

Page 112

... PIC16F627A/628A/648A NOTES: DS40044B-page 110 Preliminary  2004 Microchip Technology Inc. ...

Page 113

... INSTRUCTION SET SUMMARY Each PIC16F627A/628A/648A instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC16F627A/628A/648A instruction set summary in Table 15-2 lists byte-oriented, bit-oriented, and literal and control operations. Table 15-1 shows the opcode field descriptions. For byte-oriented instructions, ‘ ...

Page 114

... PIC16F627A/628A/648A TABLE 15-2: PIC16F627A/628A/648A INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW — Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...

Page 115

... Cycles: 1 Example ADDWF REG1, 0 Before Instruction W = 0x17 REG1 = 0xC2 After Instruction W = 0xD9 REG1 = 0xC2  2004 Microchip Technology Inc. PIC16F627A/628A/648A ANDLW k Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: . Words: Cycles: Example ANDWF Syntax: f,d Operands: Operation: Status Affected: Encoding: ...

Page 116

... PIC16F627A/628A/648A BCF Bit Clear f Syntax: [ label ] BCF f,b Operands 127 Operation: 0 (f<b>) Status Affected: None Encoding: 01 00bb Description: Bit ‘b’ in register ‘f’ is cleared Words: 1 Cycles: 1 Example BCF REG1, 7 Before Instruction REG1 = 0xC7 After Instruction REG1 = 0x47 BSF Bit Set f ...

Page 117

... FALSE GOTO TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> address FALSE if FLAG<1> address TRUE  2004 Microchip Technology Inc. PIC16F627A/628A/648A CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: Words: Cycles: REG1 PROCESS_CODE Example CLRF Syntax: ...

Page 118

... PIC16F627A/628A/648A CLRW Clear W Syntax: [ label ] CLRW Operands: None Operation: 00h ( Status Affected: Z Encoding: 00 0001 Description: W register is cleared. Zero bit (Z) is set. Words: 1 Cycles: 1 Example CLRW Before Instruction W = 0x5A After Instruction W = 0x00 CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: ...

Page 119

... Before Instruction PC = address After Instruction REG1 = REG1 - 1 if REG1 = address CONTINUE if REG1 address HERE+1  2004 Microchip Technology Inc. PIC16F627A/628A/648A GOTO Syntax: Operands: Operation: skip if result = Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example REG1, 1 LOOP HERE Preliminary ...

Page 120

... PIC16F627A/628A/648A INCF Increment f Syntax: [ label ] INCF f,d Operands 127 d [0,1] Operation: ( (dest) Status Affected: Z Encoding: 00 1010 Description: The contents of register ‘f’ are incremented. If ‘d’ the result is placed in the W register. If ‘d’ the result is placed back in register ‘f’. Words: ...

Page 121

... Words: 1 Cycles: 1 Example IORWF REG1, 0 Before Instruction REG1 = 0x13 W = 0x91 After Instruction REG1 = 0x13 W = 0x93  2004 Microchip Technology Inc. PIC16F627A/628A/648A MOVLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example MOVF f,d Syntax: Operands: Operation: Status Affected: ...

Page 122

... PIC16F627A/628A/648A MOVWF Move Syntax: [ label ] MOVWF Operands 127 Operation: (W) (f) Status Affected: None Encoding: 00 0000 Description: Move data from W register to . register ‘f’ Words: 1 Cycles: 1 Example MOVWF REG1 Before Instruction REG1 = 0xFF W = 0x4F After Instruction REG1 = 0x4F W = 0x4F NOP No Operation Syntax: ...

Page 123

... POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETURN After Interrupt PC = TOS  2004 Microchip Technology Inc. PIC16F627A/628A/648A RLF Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example ...

Page 124

... PIC16F627A/628A/648A RRF Rotate Right f through Carry Syntax: [ label ] RRF f,d Operands 127 d [0,1] Operation: See description below Status Affected: C Encoding: 00 1100 Description: The contents of register ‘f’ are rotated one bit to the right through the Carry Flag. If ‘d’ the result is placed in the W register. If ‘ ...

Page 125

... result is zero Example 3: Before Instruction REG1 = After Instruction REG1 = 0xFF result is negative  2004 Microchip Technology Inc. PIC16F627A/628A/648A SWAPF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: ...

Page 126

... PIC16F627A/628A/648A XORLW Exclusive OR Literal with W Syntax: [ label ] XORLW k Operands 255 Operation: (W) .XOR. k Status Affected: Z Encoding: 11 1010 Description: The contents of the W register are XOR’ed with the eight bit literal ‘k’. The result is placed in the W register. Words: 1 Cycles: 1 Example: XORLW 0xAF ...

Page 127

... CAN ® - PowerSmart - Analog  2004 Microchip Technology Inc. PIC16F627A/628A/648A 16.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...

Page 128

... PIC16F627A/628A/648A 16.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. ...

Page 129

... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 16.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...

Page 130

... H-Bridge motor driver, LIN transceiver and EEPROM. Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a proto- typing area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide. ...

Page 131

... Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices.  2004 Microchip Technology Inc. PIC16F627A/628A/648A 16.24 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB A microcontrollers ...

Page 132

... PIC16F627A/628A/648A NOTES: DS40044B-page 130 Preliminary  2004 Microchip Technology Inc. ...

Page 133

... Exposure to maximum rating conditions for extended periods may affect device reliability. Note: Voltage spikes below V SS Thus, a series resistor of 50-100 pulling this pin directly to V  2004 Microchip Technology Inc. PIC16F627A/628A/648A ............................................................................................-0.3 to +14V SS ....................................................................................-0. ∑ ...

Page 134

... PIC16F627A/628A/648A FIGURE 17-1: PIC16F627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40 C 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 0 Note: The shaded region indicates the permissible combinations of voltage and frequency. FIGURE 17-2: PIC16LF627A/628A/648A VOLTAGE-FREQUENCY GRAPH, -40 C 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 2.0 ...

Page 135

... DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) PIC16LF627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) PIC16F627A/628A/648A (Industrial, Extended) Param Sym Characteristic/Device No. V Supply Voltage DD D001 PIC16LF627A/628A/648A PIC16F627A/628A/648A D002 V RAM Data Retention DR (1) Voltage D003 V V Start Voltage POR DD to ensure Power-on Reset D004 S V Rise Rate VDD ...

Page 136

... PIC16F627A/628A/648A 17.2 DC Characteristics: PIC16F627A/628A/648A (Industrial) PIC16LF627A/628A/648A (Industrial) Param LF and F Device No. Characteristics Supply Voltage ( D001 LF/F Power-down Base Current ( D020 LF/F (1) Peripheral Module Current ( I ) MOD LF D021 LF/F LF/F D022 LF D023 LF/F LF D024 LF/F LF D025 LF/F Supply Current ( D010 LF/F LF D011 LF/F LF D012 ...

Page 137

... DC Characteristics: PIC16F627A/628A/648A (Extended) Param Device Characteristics No. Supply Voltage ( D001 — Power-down Base Current ( D020E — (1) Peripheral Module Current ( I ) MOD D021E — D022E — D023E — D024E — D025E — Supply Current ( D010E — D011E — D012E — D013E — Note 1: The “ ” current is the additional current consumed when this peripheral is enabled. This current should be added to the ...

Page 138

... Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. Note oscillator configuration, the OSC1 pin is a Schmitt Trigger input not recommended that the PIC16F627A/628A/648A be driven with external clock in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on applied voltage level ...

Page 139

... TABLE 17-1: DC Characteristics: PIC16F627A/628A/648A (Industrial, Extended) DC Characteristics Parameter Sym Characteristic No. Data EEPROM Memory D120 E Endurance D D120A E Endurance D D121 V V for read/write DRW DD D122 T Erase/Write cycle time DEW D123 T Characteristic Retention RETD D124 T Number of Total Erase/Write REF Cycles before Refresh Program Flash Memory ...

Page 140

... PIC16F627A/628A/648A TABLE 17-2: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V Param Characteristics No. D300 Input Offset Voltage D301 Input Common Mode Voltage D302 Common Mode Rejection Ratio (1) D303 Response Time D304 Comparator Mode Change to Output Valid * These parameters are characterized but not tested. Note 1: Response time measured with one comparator input at (V ...

Page 141

... Uppercase letters and their meanings Fall H High I Invalid (Hi-impedance) L Low FIGURE 17-3: LOAD CONDITIONS LOAD CONDITION 1 PIN R = 464 for all pins except OSC2 for OSC2 output  2004 Microchip Technology Inc. PIC16F627A/628A/648A T osc LOAD CONDITION PIN V SS Preliminary Time OSC1 T0CKI Period ...

Page 142

... PIC16F627A/628A/648A 17.6 Timing Diagrams and Specifications FIGURE 17-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 17-4: EXTERNAL CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic No. Fosc External CLKIN Frequency Oscillator Frequency 1 Tosc External CLKIN Period Oscillator Period 2 Tcy Instruction Cycle Time 3 TosL, External CLKIN (OSC1) High ...

Page 143

... T Oscillator Wake-up from Sleep IOSCST start-up time FIGURE 17-5: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O PIN (INPUT) I/O PIN OLD VALUE (OUTPUT)  2004 Microchip Technology Inc. PIC16F627A/628A/648A Min Typ Max Units — 4 — MHz — — 1 — — 2 — ...

Page 144

... PIC16F627A/628A/648A TABLE 17-6: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic No. 10 TosH2ckL OSC1 to CLKOUT 10A 11 TosH2ckH OSC1 to CLKOUT 11A 12 TckR CLKOUT rise time 12A 13 TckF CLKOUT fall time 13A 14 TckL2ioV CLKOUT to Port out valid 15 TioV2ckH Port in valid before CLKOUT 16 TckH2ioI ...

Page 145

... Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI RB6/T1OSO/T1CKI TMR0 OR TMR1  2004 Microchip Technology Inc. PIC16F627A/628A/648A V BOR 35 Min Typ† Max Units 2000 — ...

Page 146

... PIC16F627A/628A/648A TABLE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Param Sym Characteristic No. 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI Period 45 Tt1H T1CKI High Synchronous, No Prescaler Time Synchronous, with Prescaler Asynchronous PIC16F62X 46 Tt1L T1CKI Low Synchronous, No Prescaler ...

Page 147

... These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V unless otherwise stated. These parameters are for design guidance only and are not tested.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Min Typ† Max Units 0.5T + 20* — ...

Page 148

... PIC16F627A/628A/648A NOTES: DS40044B-page 146 Preliminary  2004 Microchip Technology Inc. ...

Page 149

... DC AND AC CHARACTERISTICS GRAPHS AND TABLES Not Available at this time.  2004 Microchip Technology Inc. PIC16F627A/628A/648A Preliminary DS40044B-page 147 ...

Page 150

... PIC16F627A/628A/648A NOTES: DS40044B-page 148 Preliminary  2004 Microchip Technology Inc. ...

Page 151

... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2004 Microchip Technology Inc. PIC16F627A/628A/648A EXAMPLE PIC16F627A-I/P 0210017 EXAMPLE PIC16F628A -E/SO 0210017 ...

Page 152

... PIC16F627A/628A/648A 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing § ...

Page 153

... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051  2004 Microchip Technology Inc. PIC16F627A/628A/648A Units INCHES* ...

Page 154

... PIC16F627A/628A/648A 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top ...

Page 155

... Chamfer Mold Draft Angle Top *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC equivalent: M0-220 Drawing No. C04-114  2004 Microchip Technology Inc. PIC16F627A/628A/648A EXPOSED METAL PADS ...

Page 156

... PIC16F627A/628A/648A NOTES: DS40044B-page 154 Preliminary  2004 Microchip Technology Inc. ...

Page 157

... Revised Tables 17-4 and 17-6 Corrected Table and Figure numbering in Section 17.0  2004 Microchip Technology Inc. PIC16F627A/628A/648A APPENDIX B: DEVICE DIFFERENCES The differences between the PIC16F627A/628A/648A devices listed in this data sheet are shown in Table B-1. TABLE B-1: DEVICE DIFFERENCES Device Flash Program ...

Page 158

... Code Protection for the Program Memory has changed from Code Protect sections of memory to Code Protect of the whole memory. The Configuration bits CP0 and CP1 in the PIC16F627/628 do not exist in the PIC16F627A/ 628A. They have been replaced with one Configuration bit<13> CP. 3. “Brown-out Detect (BOD)” terminology has changed to “ ...

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... MPLAB IDE: TBD ® MPLAB SIMULATOR: TBD ® MPLAB ICE 3000: PIC16F627A/628A/648A Processor Module: Part Number - TBD PIC16F627A/628A/648A Device Adapter: Socket Part Number 18-pin PDIP TBD 18-pin SOIC TBD 20-pin SSOP TBD 28-pin QFN TBD ® ...

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... PIC16F627A/628A/648A NOTES: DS40044B-page 158 Preliminary  2004 Microchip Technology Inc. ...

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... Conferences for products, Development Systems, technical information and more • Listing of seminars and events  2004 Microchip Technology Inc. PIC16F627A/628A/648A SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...

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... Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y Device: PIC16F627A/628A/648A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs you find the organization of this document easy to follow? If not, why? 4 ...

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... CCPR1L Register ............................................... 55 CCP2 .......................................................................... 55 Compare Mode. See Compare PWM Mode. See PWM Timer Resources......................................................... 55 CCP1CON Register CCP1M3:CCP1M0 Bits ............................................... 55  2004 Microchip Technology Inc. PIC16F627A/628A/648A CCP1X:CCP1Y Bits.................................................... 55 CCP2CON Register CCP2M3:CCP2M0 Bits .............................................. 55 CCP2X:CCP2Y Bits.................................................... 55 Clocking Scheme/Instruction Cycle .................................... 13 CLRF Instruction............................................................... 115 CLRW Instruction.............................................................. 116 CLRWDT Instruction......................................................... 116 Code Examples Data EEPROM Refresh Routine ...

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... PIC16F627A/628A/648A E EECON1 register ................................................................ 90 EECON2 register ................................................................ 90 Errata .................................................................................... 3 Evaluation and Programming Tools .................................. 129 External Crystal Oscillator Circuit........................................ 95 G General-Purpose Register File............................................ 15 GOTO Instruction .............................................................. 117 I I/O Ports .............................................................................. 31 Bi-Directional............................................................... 44 Block Diagrams RB0/INT Pin ........................................................ 37 RB1/RX/DT Pin ................................................... 37 RB2/TX/CK Pin ................................................... 38 RB3/CCP1 Pin .................................................... 38 RB4/PGM Pin...................................................... 39 RB5 Pin............................................................... 40 RB6/T1OSO/T1CKI Pin ...................................... 41 RB7/T1OSI Pin ...

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... TMR2 to PR2 Match ................................................... 58 Q Q-Clock ............................................................................... 59 Quick-Turnaround-Production (QTP) Devices ...................... Oscillator ....................................................................... 96 RC Oscillator Mode Block Diagram............................................................. 96 Registers Maps PIC16F627A ................................................. 16, 17 PIC16F628A ................................................. 16, 17 Reset................................................................................... 97 RETFIE Instruction............................................................ 120 RETLW Instruction ............................................................ 121 RETURN Instruction ......................................................... 121 Revision History ................................................................ 155 RLF Instruction.................................................................. 121 RRF Instruction ................................................................. 122 S Serial Communication Interface (SCI) Module, See USART Serialized Quick-Turnaround-Production (SQTP) Devices ...

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... PIC16F627A/628A/648A Sampling ......................................................... 72, 73, 74 Synchronous Master Mode ......................................... 83 Synchronous Master Reception .................................. 85 Synchronous Master Transmission............................. 83 Synchronous Slave Mode ........................................... 86 Synchronous Slave Reception .................................... 87 Synchronous Slave Transmit ...................................... 86 V Voltage Reference Configuration............................................................... 67 Voltage Reference Module.......................................... 67 W Watchdog Timer (WDT) .................................................... 106 WWW, On-Line Support........................................................ 3 X XORLW Instruction ........................................................... 124 XORWF Instruction ........................................................... 124 ...

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... PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -X Device Temperature Range Device PIC16F627A/628A/648A:Standard V PIC16F627A/628A/648ATV and Reel) PIC16LF627A/628A/648A:V PIC16LF627A/628A/648AT:V and Reel) Temperature Range Package P = PDIP SO = SOIC (Gull Wing, 300 mil body SSOP (209 mil) ...

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... Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands Biesbosch 14 NL-5152 SC Drunen, Netherlands Tel: 31-416-690399 Fax: 31-416-690340 United Kingdom 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/26/04  2004 Microchip Technology Inc. ...