PIC16F627-04/SO Microchip Technology, PIC16F627-04/SO Datasheet

IC MCU FLASH 1KX14 COMP 18SOIC

PIC16F627-04/SO

Manufacturer Part Number
PIC16F627-04/SO
Description
IC MCU FLASH 1KX14 COMP 18SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet

Specifications of PIC16F627-04/SO

Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
4MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
18-SOIC (7.5mm Width)
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
4MHz
No. Of Timers
3
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI, USART
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
16
Number Of Timers
3
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F627-04/SO
Manufacturer:
MIC
Quantity:
933
Part Number:
PIC16F627-04/SO
Manufacturer:
Microchip Technology
Quantity:
715
PIC16F62X
Data Sheet
FLASH-Based
8-Bit CMOS Microcontroller
Preliminary
 2003 Microchip Technology Inc.
DS40300C

Related parts for PIC16F627-04/SO

PIC16F627-04/SO Summary of contents

Page 1

... Microchip Technology Inc. PIC16F62X Data Sheet FLASH-Based 8-Bit CMOS Microcontroller Preliminary DS40300C ...

Page 2

... Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system ...

Page 3

... Four user programmable ID locations CMOS Technology: • Low power, high speed CMOS FLASH technology • Fully static design • Wide operating voltage range - PIC16F627 - 3.0V to 5.5V - PIC16F628 - 3.0V to 5.5V - PIC16LF627 - 2.0V to 5.5V - PIC16LF628 - 2.0V to 5.5V • Commercial, industrial and extended temperature range • ...

Page 4

... RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 SSOP RA2/AN2/V RA3/AN3/CMP1 RA4/TOCKI/CMP2 RA5/MCLR/V RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 Device Differences Device PIC16F627 PIC16F628 PIC16LF627 PIC16LF628 Note 1: If you change from this device to another device, please verify oscillator characteristics in your application. DS40300C-page 2 REF •1 18 RA1/AN1 2 17 RA0/AN0 3 ...

Page 5

... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.  2003 Microchip Technology Inc. Preliminary PIC16F62X DS40300C-page 3 ...

Page 6

... PIC16F62X NOTES: DS40300C-page 4 Preliminary  2003 Microchip Technology Inc. ...

Page 7

... FLASH devices but with all program locations and con- figuration options already programmed by the factory. Certain code and prototype verification procedures apply before production shipments are available. Please contact your Microchip Technology sales office for more details. 1.3 Serialized Quick-Turnaround Production (SQTP ...

Page 8

... PIC16F62X NOTES: DS40300C-page 6 Preliminary  2003 Microchip Technology Inc. ...

Page 9

... MHz) except for program branches. The Table below lists program memory (FLASH, Data and EEPROM). TABLE 2-1: DEVICE DESCRIPTION Memory Device FLASH RAM Program Data PIC16F627 1024 x 14 224 x 8 PIC16F628 2048 x 14 224 x 8 PIC16LF627 1024 x 14 224 x 8 PIC16LF628 2048 x 14 224 x 8 The PIC16F62X can directly or indirectly address its register files or data memory ...

Page 10

... Timer Oscillator ALU Power-on 8 Reset Watchdog W reg Timer Brown-out Detect Low-voltage Timer1 Timer2 USART Data EEPROM Preliminary PORTA RA0/AN0 RA1/AN1 RA2/AN2/V REF RA3/AN3/CMP1 RA4/T0CK1/CMP2 PP RA5/MCLR/V RA6/OSC2/CLKOUT RA7/OSC1/CLKIN PORTB RB0/INT RB1/RX/DT RB2/TX/CK RB3/CCP1 RB4/PGM RB5 RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD  2003 Microchip Technology Inc. ...

Page 11

... RB1 RX DT RB2/TX/CK RB2 TX CK RB3/CCP1 RB3 CCP1 Legend Output — = Not used TTL = TTL Input  2003 Microchip Technology Inc. Input Type Output Type ST CMOS Bi-directional I/O port AN — Analog comparator input ST CMOS Bi-directional I/O port AN — Analog comparator input ...

Page 12

... CMOS ICSP Data I/O Power — Ground reference for logic and I/O pins Power — Positive supply for logic and I/O pins CMOS = CMOS Output I = Input OD = Open Drain Output Preliminary Description P = Power ST = Schmitt Trigger Input AN = Analog  2003 Microchip Technology Inc. ...

Page 13

... PORTA, 3 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.  2003 Microchip Technology Inc. 2.2 Instruction Flow/Pipelining An “ ...

Page 14

... PIC16F62X NOTES: DS40300C-page 12 Preliminary  2003 Microchip Technology Inc. ...

Page 15

... Program Memory Organization The PIC16F62X has a 13-bit program counter capable of addressing program memory space. Only the first (0000h - 03FFh) for the PIC16F627 and (0000h - 07FFh) for the PIC16F628 are physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first space (PIC16F627 space (PIC16F628) ...

Page 16

... PIC16F62X FIGURE 3-2: DATA MEMORY MAP OF THE PIC16F627 AND PIC16F628 (1) Indirect addr. Indirect addr. 00h 01h TMR0 02h PCL STATUS 03h FSR 04h 05h PORTA PORTB 06h 07h 08h 09h PCLATH 0Ah 0Bh INTCON 0Ch PIR1 0Dh TMR1L 0Eh 0Fh TMR1H ...

Page 17

... C2OUT C1OUT Legend: — = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unimplemented Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.  2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RP0 ...

Page 18

... TX9D 69 0000 -010 69 0000 0000 87 xxxx xxxx 87 xxxx xxxx RD 87 ---- x000 87 -------- — — VR0 59 000- 0000  2003 Microchip Technology Inc. ...

Page 19

... Unimplemented Legend: — = Unimplemented locations read as ‘0’ unchanged unknown value depends on condition, shaded = unim- plemented. Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.  2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 ...

Page 20

... Microchip Technology Inc. ...

Page 21

... Legend Readable bit -n = Value at POR  2003 Microchip Technology Inc. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000uu1uu (where u = unchanged). ...

Page 22

... R/W-1 T0CS T0SE PSA TMR0 Rate WDT Rate 128 256 1 : 128 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-1 R/W-1 R/W-1 PS2 PS1 PS0 bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 23

... When at least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state Legend Readable bit -n = Value at POR  2003 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...

Page 24

... R = Readable bit -n = Value at POR DS40300C-page 22 R/W-0 R/W-0 U-0 R/W-0 RCIE TXIE — CCP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-0 R/W-0 TMR2IE TMR1IE bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 25

... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Legend Readable bit -n = Value at POR  2003 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User ...

Page 26

... OSCF ( Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary indicating a brown-out has the BODEN bit in the U-0 R/W-q R/W-q — POR BOD bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 27

... POPed in the event of a RETURN, RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.  2003 Microchip Technology Inc. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push ...

Page 28

... RAM File Registers 7Fh Bank 0 Note: For memory map detail see Figure 3-2. DS40300C-page 26 0 IRP bank select 180h Bank 1 Bank 2 Bank 3 Preliminary Indirect Addressing 7 0 FSR register location select 1FFh  2003 Microchip Technology Inc. ...

Page 29

... PIC16F62X very versatile. 4.1 Development Support The PIC16F62X family is supported by a full featured macro assembler, a software simulator, an in-circuit emulator, a low cost development programmer and a full-featured programmer. A Third Party “C” compiler support tool is also available. PIC16F627 PIC16F628 20 20 1024 2048 224 224 ...

Page 30

... PIC16F62X NOTES: DS40300C-page 28 Preliminary  2003 Microchip Technology Inc. ...

Page 31

... Note: RA5 shares function with V voltage levels are applied to RA5, the device will enter Programming mode.  2003 Microchip Technology Inc. Note 1: On RESET, the TRISA register is set to all inputs. The digital inputs are disabled and the comparator inputs are forced to ground to reduce current consumption. 2: TRISA< ...

Page 32

... TRISA D RD PORTA To Comparator Comparator Mode = 110 Preliminary BLOCK DIAGRAM OF RA2/VREF PIN RA2 Pin Analog Input Mode Schmitt Trigger Input Buffer ROE V V REF V DD RA3 Pin V SS Analog Input Mode Schmitt Trigger Input Buffer D EN  2003 Microchip Technology Inc. ...

Page 33

... BLOCK DIAGRAM OF THE RA5/MCLR/V MCLRE MCLR circuit MCLR Filter Schmitt Trigger Program Input Buffer mode HV Detect Data Bus TRISA PORTA  2003 Microchip Technology Inc. Comparator Mode = 110 FIGURE 5-6: PIN PP From OSC1 CLKOUT(F OSC / PORTA CK OSC (F = Data Latch (2) 101, 111) ...

Page 34

... Circuit CLKIN to core Data Bus PORTA CK Q Data Latch TRISA CK Q TRIS Latch RD TRISA (1) OSC F = 100, 101 RD PORTA Note 1: INTRC with CLKOUT, and INTRC with I/O. DS40300C-page Schmitt Trigger Input Buffer EN Preliminary DD V RA7/OSC1/CLKIN Pin SS V  2003 Microchip Technology Inc. ...

Page 35

... RA5 MCLR PP V RA6/OSC2/CLKOUT RA6 OSC2 XTAL CLKOUT RA7/OSC1/CLKIN RA7 OSC1 XTAL CLKIN Legend Schmitt Trigger input  2003 Microchip Technology Inc. Output Type ST CMOS Bi-directional I/O port AN — Analog comparator input ST CMOS Bi-directional I/O port AN — Analog comparator input ST CMOS ...

Page 36

... Polling of PORTB is not recommended while using the interrupt-on-change feature. Preliminary (1) Value on Value on Bit 0 All Other POR RESETS RA0 xxxx 0000 xxxu 0000 TRISA0 1111 1111 1111 1111 CM0 0000 0000 0000 0000 VR0 000- 0000 000- 0000  2003 Microchip Technology Inc. ...

Page 37

... CK Q Data Latch TRISB CK Q TRIS Latch TTL RD TRISB Input Buffer PORTB INT Schmitt Trigger  2003 Microchip Technology Inc. FIGURE 5- RBPU P Weak Pull-up PORT/PERIPHERAL Select V DD USART Data Output Data Bus RB0/INT WR PORTB TRISB (2) Peripheral OE RD TRISB RD PORTB USART Receive Input ...

Page 38

... Port/Peripheral select signal selects between port data and peripheral output. 2: Peripheral OE (output enable) is only active if peripheral select is active. Preliminary BLOCK DIAGRAM OF RB3/CCP1 PIN DD V Weak Pull-up ( RB3 CCP1 CK Q Data Latch TRIS Latch TTL Input Buffer Schmitt Trigger  2003 Microchip Technology Inc. ...

Page 39

... Data Latch D WR TRISB CK TRIS Latch RD TRISB LVP RD PORTB PGM input Set RBIF From other RB<7:4> pins Note 1: The low voltage programming disables the interrupt-on-change and the weak pull-ups on RB4.  2003 Microchip Technology Inc Schmitt Trigger Q Q Preliminary PIC16F62X V DD ...

Page 40

... PIC16F62X FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN RBPU Data Bus PORTB CK Q Data Latch TRISB CK Q TRIS Latch RD TRISB RD PORTB Set RBIF From other RB<7:4> pins DS40300C-page 38 TTL input buffer Preliminary  2003 Microchip Technology Inc weak P pull-up RB5 pin ...

Page 41

... FIGURE 5-14: BLOCK DIAGRAM OF RB6/T1OSO/T1CKI PIN RBPU Data Bus WR PORTB WR TRISB TRIS Latch RD TRISB T1OSCEN RD PORTB TMR1 Clock From RB7 Serial programming clock Set RBIF  2003 Microchip Technology Inc Data Latch Schmitt Trigger From other RB<7:4> pins Preliminary PIC16F62X V DD ...

Page 42

... Data Bus WR PORTB WR TRISB RD TRISB T10SCEN RD PORTB Serial programming input Set RBIF DS40300C-page Data Latch TRIS Latch Q Q From other RB<7:4> pins EN Preliminary DD V weak pull-up P TMR1 oscillator DD V RB7/T1OSI pin SS V TTL input buffer Schmitt Trigger  2003 Microchip Technology Inc. ...

Page 43

... RB6 86h, 186h TRISB TRISB7 TRISB6 81h, 181h OPTION RBPU INTEDG Legend unchanged unknown Note 1: Shaded bits are not used by PORTB.  2003 Microchip Technology Inc. Output Type TTL CMOS Bi-directional I/O port. Can be software programmed for internal weak pull-up. ST — ...

Page 44

... instruction cycle and propagation delay of Q1 cycle to output valid. Preliminary READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT PORTB<3:0> Outputs PORT latchPORT Pins ---------- ---------- ; ;01pp pppp 11pp pppp ; ;10pp pppp 11pp pppp ;10pp pppp 10pp pppp NOP Execute NOP  2003 Microchip Technology Inc. ...

Page 45

... Timer0 module interrupt service routine before re- enabling this interrupt. The Timer0 interrupt cannot wake the processor from SLEEP since the timer is shut off during SLEEP.  2003 Microchip Technology Inc. 6.2 Using Timer0 with External Clock When an external clock input is used for Timer0, it must meet certain requirements ...

Page 46

... The prescaler is not readable or writable SYNC 1 2 Cycles 0 T0CS PSA WDT Postscaler/ TMR0 Prescaler 8 8-to-1MUX PS0 - PS2 0 1 PSA WDT Timeout Preliminary the TMR0 register (e.g., CLRF 1, Data Bus 8 TMR0 reg Set Flag Bit T0IF on Overflow  2003 Microchip Technology Inc. ...

Page 47

... Unimplemented locations, read as ‘0’ unchanged unknown Note 1: Shaded bits are not used by TMR0 module. 2: Option is referred by OPTION_REG in MPLAB.  2003 Microchip Technology Inc. To change prescaler from the WDT to the TMR0 module use the sequence shown in Example 6-2. This precaution must be taken even if the WDT is disabled. ...

Page 48

... Timer1 also has an internal “RESET input”. This RESET can be generated by the CCP module (Section 11.0). Register 7-1 shows the Timer1 Control register. For the PIC16F627 and PIC16F628, when the Timer1 oscillator is enabled (T1OSCEN is set), the RB7/T1OSI and RB6/T1OSO/T1CKI pins become inputs. That is, the TRISB<7:6> value is ignored. ...

Page 49

... RB6/T1OSO/T1CKI RB7/T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.  2003 Microchip Technology Inc. 7.2.1 EXTERNAL CLOCK INPUT TIMING FOR SYNCHRONIZED COUNTER MODE When an external clock input is used for Timer1 in Synchronized Counter mode, it must meet certain requirements ...

Page 50

... Reading the high ; and low bytes now will read a good value. ; MOVF TMR1H, W ;Read high byte MOVWF TMPH ; MOVF TMR1L, W ;Read low byte MOVWF TMPL ; ; Re-enable the Interrupts (if required) CONTINUE ;Continue with your code Preliminary  2003 Microchip Technology Inc. ...

Page 51

... T1CKPS1 Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer1 module.  2003 Microchip Technology Inc. 7.5 Resetting Timer1 Using a CCP Trigger Output If the CCP1 module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 ...

Page 52

... TMR2IF output (1) RESET Postscaler 1:1 to 1:16 4 TOUTPS<3:0> Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. Preliminary TIMER2 BLOCK DIAGRAM Prescaler TMR2 reg OSC F /4 1:1, 1:4, 1:16 2 Comparator EQ T2CKPS<1:0> PR2 reg  2003 Microchip Technology Inc. ...

Page 53

... T2CON — 92h PR2 Timer2 Period Register Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Timer2 module.  2003 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 TOUTPS0 W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’ ...

Page 54

... PIC16F62X NOTES: DS40300C-page 52 Preliminary  2003 Microchip Technology Inc. ...

Page 55

... CM2:CM0: Comparator Mode Figure 9-1 shows the Comparator modes and CM2:CM0 bit settings Legend Readable bit -n = Value at POR  2003 Microchip Technology Inc. The CMCON register, shown in Register 9-1, controls the comparator input and output multiplexers. A block two analog diagram of the comparator is shown in Figure 9-1. ...

Page 56

... Off (Read as '0') RA0/AN0 A RA3/AN3/CMP1 A OUT C2V RA1/AN1 A RA2/AN2 Preliminary Off (Read as '0 Off (Read as '0 CIS = CIS = 1 C1V OUT CIS = CIS = 1 C2V OUT From V REF Module OUT C1V OUT C2V CIS = CIS = 1 OUT C1V OUT C2V  2003 Microchip Technology Inc. ...

Page 57

... Comparator Reference An external or internal reference signal may be used depending on the Comparator Operating mode. The IN analog signal that is present compared to the IN signal and the digital output of the comparator is adjusted accordingly (Figure 9-2).  2003 Microchip Technology Inc. FIGURE 9- ...

Page 58

... FIGURE 9-3: COMPARATOR OUTPUT BLOCK DIAGRAM CnI NV To RA3 or RA4/T0CK1 pin To Data Bus CMCON<7:6> RD CMCON Set CMIF bit From other Comparator DS40300C-page RESET Preliminary  2003 Microchip Technology Inc. CnV OUT Q1 ...

Page 59

... Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared.  2003 Microchip Technology Inc. 9.7 Comparator Operation During SLEEP When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled ...

Page 60

... CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 RCIE TXIE — CCP1IE TMR2IE TMR1IE 0000 -000 0000 -000 Preliminary IC R LEAKAGE I ±500 Value on Value on Bit 1 Bit 0 All Other POR RESETS CM1 CM0 0000 0000 0000 0000 INTF RBIF 0000 000x 0000 000u  2003 Microchip Technology Inc. ...

Page 61

... VOLTAGE REFERENCE BLOCK DIAGRAM V DD REN V 8R Vref Note defined in Table 17-2.  2003 Microchip Technology Inc. 10.1 Configuring the Voltage Reference The Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Voltage Reference are as follows ...

Page 62

... Reference module operates ROE bit, REF enabled will also increase V REF Output Value On Value On Bit 0 All Other POR RESETS VR1 VR0 000- 0000 000- 0000 CM1 CM0 0000 0000 0000 0000 TRISA0 1111 1111 1111 1111  2003 Microchip Technology Inc. ...

Page 63

... Compare mode, generate software interrupt on match (CCP1IF bit is set, CCP1 pin is unaffected) 1011 = Compare mode, trigger special event (CCP1IF bit is set; CCP1 resets TMR1 11xx = PWM mode Legend Readable bit -n = Value at POR  2003 Microchip Technology Inc. TABLE 11-1: CCP Mode Capture Compare PWM U-0 ...

Page 64

... W reg with ; the new prescaler ; mode value and CCP ON ;Load CCP1CON with this ; value COMPARE MODE OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Output Comparator Logic match TMR1H TMR1L CCP1CON<3:0> Mode Select  2003 Microchip Technology Inc. ...

Page 65

... CCP1CON — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by Capture and Timer1.  2003 Microchip Technology Inc. 11.2.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair ...

Page 66

... PWM frequency. The postscaler could be used to have an interrupt occur at a different fre- quency than the PWM output. Preliminary PWM OUTPUT Period TMR2 = PR2 TMR2 = Duty Cycle OSC • (TMR2 prescale value)  2003 Microchip Technology Inc. ...

Page 67

... CCP1CON — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by PWM and Timer2.  2003 Microchip Technology Inc. EQUATION 11-2: PWM Resolution = Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared ...

Page 68

... PIC16F62X NOTES: DS40300C-page 66 Preliminary  2003 Microchip Technology Inc. ...

Page 69

... TX9D: 9th bit of transmit data. Can be PARITY bit. Note 1: SREN/CREN overrides TXEN in SYNC mode. Legend Readable bit -n = Value at POR  2003 Microchip Technology Inc. The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) Bit SPEN (RCSTA< ...

Page 70

... R = Readable bit -n = Value at POR DS40300C-page 68 R/W-0 R/W-0 R/W-0 RX9 SREN CREN ADEN W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R-0 R-0 R-x FERR OERR RX9D bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 71

... RX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used by the BRG.  2003 Microchip Technology Inc. EXAMPLE 12-1: Desired Baud rate = F 9600 = 16000000 / (64 î25.042° Calculated Baud Rate = 16000000 / (64(25 + 1)) = 9615 Error = (Calculated Baud Rate = Desired Baud Rate) = (9615 - 9600)/ 9600 = 0 ...

Page 72

... MHz SPBRG value KBAUD ERROR (decimal) 0.303 +1.14% 26 1.170 -2.48 — — NA — — NA — — NA — — NA — — NA — — — — 8.192 — 0 0.032 — 255  2003 Microchip Technology Inc. ...

Page 73

... NA — — 300 NA — 500 NA — HIGH 55.93 — LOW 0.2185 —  2003 Microchip Technology Inc. 16 MHz SPBRG value value KBAUD ERROR (decimal) — NA — — 255 1.202 +0.16% 207 129 2.404 +0.16% 103 32 9.615 +0 ...

Page 74

... NA — — 625 — — 4 MHz SPBRG value KBAUD ERROR (decimal) 9615.385 0.160% 25 19230.77 0.160% 12 35714.29 -6.994% 6 62500 8.507% 3 125000 8.507% 1 250000 0.000 — — NA — — 32.768 MHz SPBRG value KBAUD ERROR (decimal  2003 Microchip Technology Inc. ...

Page 75

... RX pin baud clk x4 clk Q2, Q4 clk FIGURE 12-3: RX PIN SAMPLING SCHEME, BRGH = 1 RX pin Baud CLK First falling edge after RX pin goes low x4 CLK Q2, Q4 CLK  2003 Microchip Technology Inc. START bit Baud CLK for all but START bit Samples ...

Page 76

... TXREG register. This is because a data write to the TXREG register can result in an immediate transfer of the data to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register. Preliminary Bit0  2003 Microchip Technology Inc. ...

Page 77

... BRG output (shift clock) RB2/TX/CK (pin) START Bit TXIF bit (Transmit buffer reg. empty flag) WORD 1 TRMT bit Transmit Shift Reg (Transmit shift reg. empty flag)  2003 Microchip Technology Inc. Data Bus TXREG register 8 MSb LSb ( TSR register TRMT TX9 ...

Page 78

... Transmit Shift Reg. Value on Value on Bit 0 all other POR RESETS TMR1IF 0000 -000 0000 -000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -000 0000 -000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000  2003 Microchip Technology Inc. ...

Page 79

... ADEN RX9 ADEN RSR<8>  2003 Microchip Technology Inc possible for two bytes of data to be received and transferred to the RCREG FIFO, and a third byte begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA< ...

Page 80

... BIT8 = 1, ADDRESS BYTE START STOP BIT8 STOP BIT BIT0 BIT8 BIT BIT WORD 1 BIT8 = 0, DATA BYTE RCREG START STOP BIT8 STOP BIT BIT0 BIT8 BIT BIT WORD 1 BIT8 = 0, DATA BYTE RCREG Preliminary WORD 1 RCREG '1' '1' WORD 2 RCREG  2003 Microchip Technology Inc. ...

Page 81

... EEIE CMIE 98h TXSTA CSRC TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.  2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RCIF TXIF — CCP1IF TMR2IF TMR1IF 0000 -000 0000 -000 ...

Page 82

... BRGH TRMT Preliminary enabled by setting bit CREN Value on Value on Bit 1 Bit 0 all other POR RESETS RX9D 0000 -00x 0000 -00x RX1 RX0 0000 0000 0000 0000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000  2003 Microchip Technology Inc. ...

Page 83

... TXREG register will result in an immediate transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible.  2003 Microchip Technology Inc. Clearing enable bit TXEN, during a transmission, will cause the transmission to be aborted and will RESET the transmitter. The DT and CK pins will revert to hi- impedance ...

Page 84

... Preliminary Value on all Value on Bit 0 other POR RESETS 0000 -000 RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 -000 TX9D 0000 -010 0000 -010 0000 0000 0000 0000 Bit 1 Bit 7 WORD 2 '1' Bit6 Bit7  2003 Microchip Technology Inc. ...

Page 85

... SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.  2003 Microchip Technology Inc. receive bit is buffered the same way as the receive data. Reading the RCREG register, will load bit RX9D ...

Page 86

... If interrupts are desired, then set enable bit TXIE 9-bit transmission is desired, then set bit TX9. 5. Enable the transmission by setting enable bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. Preliminary BIT6 BIT7 '0'  2003 Microchip Technology Inc. ...

Page 87

... TX9 99h SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.  2003 Microchip Technology Inc. setting bits SYNC and SPEN and clearing bit CSRC interrupts are desired, then set enable bit RCIE ...

Page 88

... PIC16F62X NOTES: DS40300C-page 86 Preliminary  2003 Microchip Technology Inc. ...

Page 89

... The inability to clear the WR bit in software prevents the accidental, premature termination of a write operation.  2003 Microchip Technology Inc. The EEPROM data memory allows byte read and write. A byte write automatically erases the location and writes the new data (erase before write). The EEPROM data memory is rated for high erase/write cycles ...

Page 90

... R = Readable bit -n = Value at POR DS40300C-page 88 U-0 U-0 U-0 R/W-x — — — WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ’1’ = Bit is set ’0’ = Bit is cleared Preliminary R/W-0 R/S-0 R/S-x WREN WR RD bit Bit is unknown  2003 Microchip Technology Inc. ...

Page 91

... After a write sequence has been initiated, clearing the WREN bit will not affect this write cycle. The WR bit will be inhibited from being set unless the WREN bit is set.  2003 Microchip Technology Inc. At the completion of the write cycle, the WR bit is cleared in hardware and the EE Write Complete Interrupt Flag bit (EEIF) is set ...

Page 92

... Shaded cells are not used by data EEPROM. Note 1: EECON2 is not a physical register DS40300C-page 90 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — WRERR WREN WR Preliminary Value on Value on all Bit 0 Power-on other Reset RESETS xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RD ---- x000 ---- q000 ---- ---- ---- ----  2003 Microchip Technology Inc. ...

Page 93

... The ER oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.  2003 Microchip Technology Inc. 14.1 Configuration Bits The configuration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device configurations ...

Page 94

... When MCLR is asserted in INTRC or ER mode, the internal clock oscillator is disabled. Legend R = Readable bit W = Writable bit -n = Value at POR 1 = bit is set DS40300C-page 92 CPD LVP BODEN MCLRE FOSC2 (1) DD (1) ( Unimplemented bit, read as ‘0’ bit is cleared Preliminary PWRTE WDTE F0SC1 F0SC0 bit bit is unknown  2003 Microchip Technology Inc. ...

Page 95

... RS NOTE 1 C2 Note 1: A series resistor may be required for some crys- tals. 2: See Table 14-1 and Table 14-2 for recommended values of C1 and C2.  2003 Microchip Technology Inc. TABLE 14-1: Ranges Characterized: Mode Freq XT 455 kHz 2.0 MHz 4.0 MHz HS 8.0 MHz 16 ...

Page 96

... EXT values below EXT values (e.g., 1M), the EXT EXTERNAL RESISTOR RA7/OSC1/CLKIN RA6/OSC2/CLKOUT RESISTANCE AND FREQUENCY RELATIONSHIP Frequency 10.4 MHz 10 MHz 7.4 MHz 5.3 MHz 3 MHz 1.6 MHz 800 kHz 300 kHz 200 kHz OSC signal (internal  2003 Microchip Technology Inc. ...

Page 97

... CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter OSC Note 1: This is a separate oscillator from the INTRC/ER oscillator.  2003 Microchip Technology Inc. 14.4 RESET The PIC16F62X differentiates between various kinds of RESET: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during SLEEP ...

Page 98

... BOD for longer than T BOD , the DD BOD falls below V for BOD BOD BOD . V and T are defined in DD rises above BOD while the Power-up Timer is BOD , the Power-Up Timer will BOD V BOD V BOD V  2003 Microchip Technology Inc. ...

Page 99

... Note 1: Other (non Power-up) Resets include MCLR Reset, Brown-out Detect Reset and Watchdog Timer Reset during normal opera- tion.  2003 Microchip Technology Inc. 14.5.6 POWER CONTROL (PCON) STATUS REGISTER The Power Control/STATUS register, PCON (address 8Eh) has two bits. ...

Page 100

... (4) uuuq quuu uuuu uuuu xxxx 0000 uuuu uuuu --uu uuuu -uuu uuuu --uu uuuu uuuu -uuu uu-- uuuu ---u uuuu (2) uuuu uqqq (2,5) -q-- ---- uuuu uuuu uu-u uuuu uuuu uuuu uuuu -uuu ---- --uu uuuu -uuu ---- uuuu uuu- uuuu  2003 Microchip Technology Inc. ...

Page 101

... DD MCLR INTERNAL POR PWRT TIMEOUT OST TIMEOUT INTERNAL RESET FIGURE 14-10: TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIMEOUT OST TIMEOUT INTERNAL RESET  2003 Microchip Technology Inc. Tpwrt Tost Tpwrt Tost Tpwrt Tost Preliminary PIC16F62X ): CASE DD ): CASE DS40300C-page 99 ...

Page 102

... Transistor Q1 turns off when V below a certain level such that Internal Brown-out Detect Reset should be disabled when using this circuit. Vdd x 3: Resistors should be adjusted for the characteristics of the transistor. DD Preliminary MCLR 40k PIC16F62X 0. 0  2003 Microchip Technology Inc. ...

Page 103

... TXIE RCIF RCIE EEIF EEIE  2003 Microchip Technology Inc. When an interrupt is responded to, the GIE is cleared to disable any further interrupt, the return address is pushed into the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt flag bits ...

Page 104

... COMPARATOR INTERRUPT See Section 9.6 for complete description of comparator interrupts (1) (2) Interrupt Latency PC+1 PC+1 Inst (PC+1) — Dummy Cycle Inst (PC) Preliminary by setting/clearing T0IE 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) Dummy Cycle  2003 Microchip Technology Inc. ...

Page 105

... STATUS_TEMP,W ;swap STATUS_TEMP register into W, sets bank to origi- nal state MOVWF STATUS ;move W into STATUS register SWAPF W_TEMP,F ;swap W_TEMP SWAPF W_TEMP,W ;swap W_TEMP into W  2003 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 T0IE INTE RBIE T0IF INTF RCIF TXIF — ...

Page 106

... Preliminary PS<2:0> TMR0 (Figure 6-1) PSA Value on all Value on Bit 0 other POR Reset RESETS FOSC0 uuuu uuuu uuuu uuuu PS0 1111 1111 1111 1111 with no external REF should be disabled. I/O pins that DD or IHMC ).  2003 Microchip Technology Inc. ...

Page 107

... The INTRC calibration data is not erased.  2003 Microchip Technology Inc. corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device con- tinues execution at the instruction after the instruction ...

Page 108

... V IHH on MCLR. The LVP bit cannot be programmed when programming is entered with RB4/ PGM. It should be noted, that once the LVP bit is programmed to 0, High voltage Programming mode can be used to program the device. PP Preliminary IHH to IHH IHH  2003 Microchip Technology Inc. ...

Page 109

... Register bit field ∈ In the set of italics User defined term (font is courier)  2003 Microchip Technology Inc. The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations All instructions are executed within one single ...

Page 110

... TO,PD 00 0000 0110 0100 10 1kkk kkkk kkkk Z 11 1000 kkkk kkkk 11 00xx kkkk kkkk 00 0000 0000 1001 11 01xx kkkk kkkk 00 0000 0000 1000 TO,PD 00 0000 0110 0011 C,DC,Z 11 110x kkkk kkkk Z 11 1010 kkkk kkkk  2003 Microchip Technology Inc ...

Page 111

... Words: 1 Cycles: 1 Example ADDWF REG1, 0 Before Instruction W = 0x17 REG1 = 0xC2 After Instruction W = 0xD9 REG1 = 0xC2  2003 Microchip Technology Inc. ANDLW k Syntax: Operands: Operation: Status Affected: kkkk kkkk Encoding: Description: Words: Cycles: Example ANDWF Syntax: f,d Operands: Operation: Status Affected: Encoding: ...

Page 112

... NOP is executed instead, making this a two-cycle instruction. 1 (2) 1 HERE BTFSC REG1 FALSE GOTO PROCESS_CODE TRUE • • • Before Instruction PC = address HERE After Instruction if REG<1> address TRUE if REG<1>= address FALSE  2003 Microchip Technology Inc. ...

Page 113

... BTFSS FALSE GOTO TRUE • • • Before Instruction PC = address HERE After Instruction if FLAG<1> address FALSE if FLAG<1> address TRUE  2003 Microchip Technology Inc. CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: Words: Cycles: REG1 PROCESS_CODE Example CLRF Syntax: ...

Page 114

... DECF f,d 0 ≤ f ≤ 127 d ∈ [0,1] ( → (dest 0011 dfff ffff Decrement register 'f the result is stored in the W register the result is stored back in register 'f DECF CNT, 1 Before Instruction CNT = 0x01 After Instruction CNT = 0x00  2003 Microchip Technology Inc. ...

Page 115

... CONTINUE • • • Before Instruction PC = address After Instruction REG1 = REG1 - 1 if REG1 = address CONTINUE if REG1 ≠ address HERE+1  2003 Microchip Technology Inc. GOTO Syntax: Operands: Operation: skip if result = Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example REG1, 1 LOOP ...

Page 116

... A NOP is executed instead making it a two-cycle instruction. 1 (2) 1 HERE INCFSZ REG1, 1 GOTO LOOP CONTINUE • • • Before Instruction PC = address HERE After Instruction REG1 = REG1 + 1 if CNT = address CONTINUE if REG1≠ address HERE +1  2003 Microchip Technology Inc. ...

Page 117

... Words: 1 Cycles: 1 Example IORWF REG1, 0 Before Instruction REG1 = 0x13 W = 0x91 After Instruction REG1 = 0x13 W = 0x93  2003 Microchip Technology Inc. MOVLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: Example MOVF f,d Syntax: Operands: Operation: Status Affected: ...

Page 118

... GIE None 00 0000 0000 1001 Return from Interrupt. Stack is POPed and Top of Stack (TOS) is loaded in the PC. Interrupts are enabled by setting Global Interrupt Enable bit, GIE (INTCON<7>). This is a two- cycle instruction RETFIE After Interrupt PC = TOS GIE = 1  2003 Microchip Technology Inc. ...

Page 119

... POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction. Words: 1 Cycles: 2 Example RETURN After Interrupt PC = TOS  2003 Microchip Technology Inc. RLF Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: Words: Cycles: ...

Page 120

... The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register SUBLW 0x02 Before Instruction After Instruction result is positive Before Instruction After Instruction result is zero Before Instruction After Instruction W = 0xFF result is negative  2003 Microchip Technology Inc. ...

Page 121

... REG1 = result is zero Example 3: Before Instruction REG1 = After Instruction REG1 = 0xFF result is negative  2003 Microchip Technology Inc. SWAPF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles: Example TRIS Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: ...

Page 122

... Z 00 0110 dfff ffff Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f XORWF REG1, 1 Before Instruction REG1 = 0xAF W = 0xB5 After Instruction REG1 = 0x1A W = 0xB5  2003 Microchip Technology Inc. ...

Page 123

... PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog  2003 Microchip Technology Inc. 16.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...

Page 124

... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high speed simulator is designed to debug, analyze and optimize time intensive DSP routines. (trigonometric, Preliminary excellent, economical software  2003 Microchip Technology Inc. ...

Page 125

... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application.  2003 Microchip Technology Inc. 16.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low cost, run-time development tool, connecting to the host PC via an RS-232 or high speed USB interface ...

Page 126

... The PICDEM 17 demonstration board supports program download and execution from external on-board FLASH memory. A generous prototype area is available for user hardware expansion. Preliminary and PIC18FXX2 devices. All the PIC17C762 and PIC17C766.  2003 Microchip Technology Inc. A ...

Page 127

... LIN transceivers. A PIC16F874 FLASH microcontroller serves as the master. All three microcontrollers are programmed with firmware to provide LIN bus communication.  2003 Microchip Technology Inc. 16.21 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...

Page 128

... DEVELOPMENT TOOLS FROM MICROCHIP dsPIC30F PIC18FXXX PI18CX01 PIC18CXX2 PIC17C7XX PIC17C4X PIC16C9XX PIC16F8XX PIC16C8X PIC16C7X5 PIC16C7XX PIC16C7X PIC16F62X PIC16C43X PIC16CXXX PIC16C6X PIC16C5X PIC14000 PIC12FXXX PIC12CXXX Tools Software Emulators Debugger Programmers DS40300C-page 126 Kits Eval and Boards Preliminary  2003 Microchip Technology Inc. Demo ...

Page 129

... Note: Voltage spikes below the MCLR pin, inducing currents greater than 80 mA, may cause latchup. Thus, Ω a series resistor of 50-100 SS this pin directly to V  2003 Microchip Technology Inc. SS ............................................................................................-0.3 to +14V SS ....................................................................................-0. )..................................................................................................................... ± )............................................................................................................... ± ∑ I ...

Page 130

... PIC16F62X VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA < 0°C, +70°C < TA ≤ 85°C FIGURE 17-2: 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency. DS40300C-page 128 4 10 FREQUENCY (MHz FREQUENCY (MHz) Preliminary  2003 Microchip Technology Inc. ...

Page 131

... TA < 0°C, +70°C < TA ≤ 85°C 6.0 5.5 5.0 4 (VOLTS) 4.0 3.5 3.0 2.5 2.0 0 Note 1: The shaded region indicates the permissible combinations of voltage and frequency.  2003 Microchip Technology Inc FREQUENCY (MHz FREQUENCY (MHz) Preliminary PIC16F62X DS40300C-page 129 ...

Page 132

... Fosc = 20.0 MHz 5.5 mA Fosc = 20.0 MHz 4.5* (6) OSC 10.0 MHz 3.0 µA OSC kHz 2 Fosc = 4.0 MHz 3 Fosc = 4.0 MHz 5.5* OSC 20.0 MHz 5.5 OSC 20.0 MHz 4.5* (6) OSC 10.0 MHz 3.0* µA OSC kHz 3.  2003 Microchip Technology Inc. ...

Page 133

... For RC osc configuration, current through R formula /2R EXT (mA) with R  2003 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) -40°C ≤ Ta ≤ +85°C for industrial and Operating temperature 0°C ≤ Ta ≤ +70°C for commercial Standard Operating Conditions (unless otherwise stated) -40°C ≤ Ta ≤ +85°C for industrial and Operating temperature 0° ...

Page 134

... =-3.0 mA, V =4.5V, -40° to +85° =-2.5 mA, V =4.5V, +125° =-1.3 mA =4.5V, -40° to +85° =-1.0 mA, V =4.5V, +125°C V RA4 pin PIC16F62X, PIC16LF62X XT, HS and LP modes when external clock used to drive OSC1. pF  2003 Microchip Technology Inc. ...

Page 135

... Unit Resistor Value (R) (1) 310* Settling Time * These parameters are characterized but not tested. Note 1: Settling time measured while VRR = 1 and VR<3:0> transitions from 0000 to 1111.  2003 Microchip Technology Inc. <5.5V, -40°C < < +125°C, unless otherwise stated. Sym Min ...

Page 136

... Invalid (Hi-impedance) L Low FIGURE 17-5: LOAD CONDITIONS Load Condition 1 PIN 464Ω for all pins except OSC2 15 pF for OSC2 output DS40300C-page 134 T osc Load Condition PIN V SS Preliminary Time OSC1 T0CKI Period Rise Valid Hi-Impedance  2003 Microchip Technology Inc. ...

Page 137

... Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 17.4 Timing Diagrams and Specifications FIGURE 17-6: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT  2003 Microchip Technology Inc. Standard Operating Conditions (unless otherwise stated) Min Typ† Max 1M 10M — * ...

Page 138

... XT and ER Osc mode ns HS Osc mode µs LP Osc mode ns ER Osc mode ns XT Osc mode ns HS Osc mode µs LP Osc mode ns INTRC mode (fast) µs INTRC mode (slow 4/F OSC OSC ns XT oscillator, T L/H duty cycle*  2003 Microchip Technology Inc. ...

Page 139

... OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time) * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2003 Microchip Technology Inc ...

Page 140

... TBD TBD TBD ms µs — — 2.0 µs 100 — — Preliminary  2003 Microchip Technology Inc. 34 Conditions 5V, -40°C to +85°C Extended temperature 5V, -40°C to +85°C Extended temperature OSC T = OSC1 period 5V, -40°C to +85°C Extended temperature ≤ ...

Page 141

... FIGURE 17-10: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI RB6/T1OSO/T1CKI TMR0 OR TMR1  2003 Microchip Technology Inc Preliminary PIC16F62X 48 DS40300C-page 139 ...

Page 142

... N = prescale value ( — — — — — ns — — ns — 200 kHz — 7Tosc —  2003 Microchip Technology Inc. ...

Page 143

... Tt0P T0CKI Period * These parameters are characterized but not tested. † Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.  2003 Microchip Technology Inc. Min Typ† Max Units CY 0. — ...

Page 144

... PIC16F62X NOTES: DS40300C-page 142 Preliminary  2003 Microchip Technology Inc. ...

Page 145

... The graphs and tables provided in this sec- tion are for design guidance and are not tested. FIGURE 18-1: TYPICAL  2003 Microchip Technology Inc OVER V – HS MODE OSC DD Typical: Maximum: mean + 3σ (-40°C to 125°C) Typical over V DD OSC DD Minimum: (HS mode) 5 ...

Page 146

... Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125° Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) PIC16LF628 Minimum: mean – 3σ (-40°C to 125°C) 3.0 3.5 4.0  2003 Microchip Technology Inc. ...

Page 147

... DD VS 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.0 0.5 1.0 FIGURE 18-5: TYPICAL 3. 30.000 40.000  2003 Microchip Technology Inc. F OVER V (XT MODE) OSC DD Typical over (XT m ode) 5.5V 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 1.5 2.0 2 ...

Page 148

... Maximum: mean + 3σ (-40°C to 125°C) PIC16LF628 Minimum: mean – 3σ (-40°C to 125°C) 80.000 90.000 100.000 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 4.5 5.0  2003 Microchip Technology Inc. ...

Page 149

... FIGURE 18-9: TYPICAL INTERNAL RC F INTERNAL 37 kHz OSCILLATOR 60.000 50.000 125 40.000 25 C -40 C 30.000 20.000 10.000 0.000 2.0 2.5  2003 Microchip Technology Inc. V TEMPERATURE (-40 TO 125°C) OSC VS DD Typical Internal RC F OSC over 25 C -40 C 3.0 3.5 4.0 V ...

Page 150

... Max (125C) Max (85C) Typ (25C) 4.5 5.0 5.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Max Typ Sleep (25C) Device in Sleep 4.5 5.0 5.5  2003 Microchip Technology Inc. ...

Page 151

... Microchip Technology Inc. V OVER TEMP (0C to +70°C) DD ∆I TMR1OSC over Temp (0C to +70C) Sleep mode, Timer1 oscillator, 32 kHz XTAL 3.0 3.5 4.0 V (V) DD SLEEP MODE, WATCH DOG TIMER ENABLED ∆ ...

Page 152

... Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 4.5 5.0 5.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Max (125C) Typ (25C) 4.5 5.0 5.5  2003 Microchip Technology Inc. ...

Page 153

... FIGURE 18-17: TYPICAL WDT PERIOD 2.0 2.5  2003 Microchip Technology Inc. Minimum, Typical and Maximum WDT Period (-40C to +125C) Max 125C Max 85C Typ 25C Min -40C 3.0 3.5 4 (-40°C to +125° Typical WDT Period (-40C to +125C) 3 ...

Page 154

... Minimum: mean – 3σ (-40°C to 125°C) Max (-40C) Typ (25C) Min (125C) 20.0 25.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Max (-40C) 12.0 14.0  2003 Microchip Technology Inc. ...

Page 155

... FIGURE 18-21 OVER TEMP ( 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 0.0 5.0  2003 Microchip Technology Inc Typical: Maximum: mean + 3σ (-40°C to 125° over Temp ( Minimum 10.0 15.0 I (mA Typical: Maximum: mean + 3σ (-40°C to 125°C) ...

Page 156

... Min (125C) 4.5 5.0 5.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) Max High (125C) Min High (-40C) Max Low (125C) Min Low (-40C) 4.5 5.0 5.5  2003 Microchip Technology Inc. ...

Page 157

... TYPICAL IDD VS VDD OVER TEMPERATURE (-40 TO +125°C) INTERNAL 37 kHz OSCILLATOR 35.000 30.000 25.000 125 20.000 25 C -40C 15.000 10.000 2.5 3.0  2003 Microchip Technology Inc. V OVER TEMPERATURE DD Maximum over Temperature DD DD (-40 to +125 C) Internal 37kHz Oscillator 125 3.5 4.0 4 ...

Page 158

... PIC16LF628 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.0 5.5 Typical: statistical mean @ 25°C PIC16LF628 Maximum: mean + 3σ (-40°C to 125°C) Minimum: mean – 3σ (-40°C to 125°C) 5.0 5.5  2003 Microchip Technology Inc. ...

Page 159

... Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.  2003 Microchip Technology Inc. EXAMPLE PIC16F628/P ...

Page 160

... L p MILLIMETERS MIN NOM MAX 18 2.54 3.56 3.94 4.32 2.92 3.30 3.68 0.38 7.62 7.94 8.26 6.10 6.35 6.60 22.61 22.80 22.99 3.18 3.30 3.43 0.20 0.29 0.38 1.14 1.46 1.78 0.36 0.46 0.56 7.87 9.40 10.  2003 Microchip Technology Inc. ...

Page 161

... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051  2003 Microchip Technology Inc φ Units ...

Page 162

... Preliminary α A2 MILLIMETERS MIN NOM MAX 20 0.65 1.73 1.85 1.98 1.63 1.73 1.83 0.05 0.15 0.25 7.59 7.85 8.18 5.11 5.25 5.38 7.06 7.20 7.34 0.56 0.75 0.94 0.10 0.18 0.25 0.00 101.60 203.20 0.25 0.32 0.  2003 Microchip Technology Inc. ...

Page 163

... Clocking Scheme/Instruction Cycle .................................... 11 CLRF Instruction ............................................................... 111 CLRW Instruction .............................................................. 112 CLRWDT Instruction ......................................................... 112 Code Protection ................................................................ 105 COMF Instruction .............................................................. 112 Comparator Configuration................................................... 54  2003 Microchip Technology Inc. Comparator Interrupts......................................................... 57 Comparator Module ............................................................ 53 Comparator Operation ........................................................ 55 Comparator Reference ....................................................... 55 Compare (CCP Module) ..................................................... 62 Block Diagram ............................................................ 62 CCP Pin Configuration ............................................... 62 CCPR1H:CCPR1L Registers ...

Page 164

... Software Simulator (MPLAB SIM) .................................... 122 Special ................................................................................ 95 Special Event Trigger. See Compare Special Features of the CPU .............................................. 91 Special Function Registers ................................................. 15 Stack................................................................................... 25 Status Register ................................................................... 19 SUBLW Instruction ........................................................... 118 SUBWF Instruction ........................................................... 119 SWAPF Instruction ........................................................... 119 T T1CKPS0 bit ....................................................................... 46 T1CKPS1 bit ....................................................................... 46 T1OSCEN bit ...................................................................... 46 Preliminary  2003 Microchip Technology Inc. ...

Page 165

... Setting Up Reception .......................................... 80 Timing Diagram .................................................. 78 Asynchronous Receiver Mode Block Diagram .................................................... 80 Section ................................................................ 80 USART Asynchronous Mode ................................................... 74 Asynchronous Receiver .............................................. 77  2003 Microchip Technology Inc. Asynchronous Reception............................................ 79 Asynchronous Transmission....................................... 75 Asynchronous Transmitter.......................................... 74 Baud Rate Generator (BRG) ...................................... 69 Sampling......................................................... 70, 71, 72 Synchronous Master Mode......................................... 81 Synchronous Master Reception ................................. 83 Synchronous Master Transmission ............................ 81 Synchronous Slave Mode ...

Page 166

... PIC16F62X NOTES: DS40300C-page 164 Preliminary  2003 Microchip Technology Inc. ...

Page 167

... Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events  2003 Microchip Technology Inc. SYSTEMS INFORMATION AND UPGRADE HOT LINE The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products ...

Page 168

... What deletions from the document could be made without affecting the overall usefulness there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS40300C-page 166 Total Pages Sent ________ FAX: (______) _________ - _________ N Literature Number: DS40300C Preliminary  2003 Microchip Technology Inc. ...

Page 169

... Microchip Technology Inc. /XX XXX Examples: a) Package Pattern b) DD range 3.0V to 5.5V +70°C +85°C +125°C Preliminary PIC16F62X PIC16F627 - 04/P 301 = Commercial Temp PDIP package, 4 MHz, normal limits, QTP pattern #301. PIC16LF627 - 04I/SO = Industrial Temp SOIC package, 200 kHz, extended limits. DS40300C-page167 ...

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... Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan Microchip Technology (Barbados) Inc., Taiwan Branch 11F-3, No ...

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