PIC16F627-04/SO Microchip Technology, PIC16F627-04/SO Datasheet - Page 107

• Manufacturer Part Number: PIC16F627-04/SO
• Description: IC MCU FLASH 1KX14 COMP 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F627-04/SO

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 4MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC (7.5mm Width)
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 224Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 3 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT18SO-1 - SOCKET TRANSITION 18SOIC 300MILAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Lead Free Status / Rohs Status: Details

14.9.1
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
The first event will cause a device RESET. The two
latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
When the
next instruction (PC + 1) is pre-fetched. For the device
to
FIGURE 14-17:
14.10 Code Protection
If
programmed, the on-chip program memory can be
read out for verification purposes.
 2003 Microchip Technology Inc.
Note
OSC1
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
Note:
the
External RESET input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin, RB Port change, or
the Peripheral Interrupt (Comparator).
wake-up
1: XT, HS or LP Oscillator mode assumed.
2: T
3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue
4: CLKOUT is not available in these Osc modes, but shown here for timing reference.
(4)
PC
code
SLEEP
in-line.
The entire data EEPROM and FLASH
program memory will be erased when the
code protection is turned off. The INTRC
calibration data is not erased.
WAKE-UP FROM SLEEP
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
= 1024T
through
Inst(PC - 1)
protection
PC
instruction is being executed, the
OSC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
an
(drawing not to scale). Approximately 1 µs delay will be there for ER Osc mode.
bit(s)
Inst(PC + 1)
SLEEP
PC+1
interrupt
have
Processor in
event,
SLEEP
not
PC+2
been
Preliminary
the
Tost
(2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
(Note 2)
corresponding interrupt enable bit must be set
(enabled). Wake-up is regardless of the state of the
GIE bit. If the GIE bit is clear (disabled), the device con-
tinues execution at the instruction after the
instruction. If the GIE bit is set (enabled), the device
executes the instruction after the
and then branches to the interrupt address (0004h). In
cases where the execution of the instruction following
SLEEP
after the
The WDT is cleared when the device wakes-up from
SLEEP, regardless of the source of wake-up.
14.11 User ID Locations
Four memory locations (2000h-2003h) are designated
as user ID locations where the user can store
checksum or other code-identification numbers. These
locations are not accessible during normal execution
but are readable and writable during program/verify.
Only the Least Significant 4 bits of the user ID locations
are used.
PC+2
Note:
is not desirable, the user should have an
SLEEP
Dummy cycle
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the correspond-
ing interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
PC + 2
instruction.
Inst(0004h)
Dummy cycle
PIC16F62X
0004h
DS40300C-page 105
SLEEP
Inst(0005h)
Inst(0004h)
0005h
instruction
SLEEP
NOP