PIC18F13K50-I/SS Microchip Technology, PIC18F13K50-I/SS Datasheet - Page 190

• Manufacturer Part Number: PIC18F13K50-I/SS
• Description: IC PIC MCU FLASH 8KB 20-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPAC164307 - MODULE SKT FOR PM3 28SSOP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F/LF1XK50
16.2
The factory calibrates the internal oscillator block out-
put (HFINTOSC). However, the HFINTOSC frequency
may drift as V
directly affects the asynchronous baud rate. Two meth-
ods may be used to adjust the baud rate clock, but both
require a reference clock source of some kind.
REGISTER 16-1:
DS41350E-page 190
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0
CSRC
Clock Accuracy with
Asynchronous Operation
SREN/CREN overrides TXEN in Sync mode.
DD
CSRC: Clock Source Select bit
Asynchronous mode:
Don’t care
Synchronous mode:
1 =
0 =
TX9: 9-bit Transmit Enable bit
1 =
0 =
TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SYNC: EUSART Mode Select bit
1 = Synchronous mode
0 = Asynchronous mode
SENDB: Send Break Character bit
Asynchronous mode:
1 = Send Sync Break on next transmission (cleared by hardware upon completion)
0 = Sync Break transmission completed
Synchronous mode:
Don’t care
BRGH: High Baud Rate Select bit
Asynchronous mode:
1 = High speed
0 = Low speed
Synchronous mode:
Unused in this mode
TRMT: Transmit Shift Register Status bit
1 = TSR empty
0 = TSR full
TX9D: Ninth bit of Transmit Data
Can be address/data bit or a parity bit.
or temperature changes, and this
R/W-0
TX9
Master mode (clock generated internally from BRG)
Slave mode (clock from external source)
Selects 9-bit transmission
Selects 8-bit transmission
TXSTA: TRANSMIT STATUS AND CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
TXEN
R/W-0
(1)
(1)
R/W-0
SYNC
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SENDB
R/W-0
The first (preferred) method uses the OSCTUNE
register to adjust the HFINTOSC output. Adjusting the
value in the OSCTUNE register allows for fine resolution
changes to the system clock source. See
“OSCTUNE Register”
The other method adjusts the value in the Baud Rate
Generator. This can be done automatically with the
Auto-Baud
“Auto-Baud
resolution when adjusting the Baud Rate Generator to
compensate for a gradual change in the peripheral
clock frequency.
Detect
Detect”). There may not be fine enough
BRGH
R/W-0
feature
for more information.
 2010 Microchip Technology Inc.
x = Bit is unknown
TRMT
R-1
(see
Section 16.3.1
Section 2.6.1
R/W-0
TX9D
bit 0