PIC18F24K20-I/SP Microchip Technology, PIC18F24K20-I/SP Datasheet - Page 2
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PIC18F24K20-I/SP
Manufacturer Part Number
PIC18F24K20-I/SP
Description
IC PIC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F24K20-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F24K20/25K20/44K20/45K20
TABLE 2:
DS80425G-page 2
ECCP
ECCP
MSSP SPI
MSSP I
ADC
MSSP I
MSSP I
MSSP SPI
MSSP SPI
MSSP SPI
EUSART
EUSART
EUSART
Internal Fixed
Voltage Refer-
ence (FVR)
High Low Voltage
Detect (HLVD)
BOR
System Clocks
POR/BOR
POR
POR
Clocks
Comparators
Data EEPROM
Memory
Program Flash
Memory
Configuration Bits
Note 1:
Module
2:
2
2
2
C™
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Shaded cells in this table indicate older device revisions that are no longer in production.
SILICON ISSUE SUMMARY
CCP1CON
Full-Bridge
mode
SPI Clock
Slew Rate
Offset
Receiving
Master mode
SPI Master
SPI Master
SPI Master
Synchronous
Master mode
Synchronous
Master mode
Synchronous
Master mode
FVR
EC mode
Interrupt-on-
Change
Endurance
Endurance
CONFIG3H
Feature
—
—
—
—
—
—
Number
Item
10.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
11.
1.
2.
4.
5.
6.
7.
3.
8.
9.
Changing CCP1M bits may
cause capture of Timer1 value.
Direction change issue.
Shortened SPI high time.
Slow slew rate when
SLRCON<2> is set.
Time dependent on offset.
Address may be received as
data.
Master mode not functional.
Improper sampling of last bit.
SSPBUF improperly reloads on
SS pin transitions.
Improper extra pulse on SCK
pin.
Duty cycle of CK output is
skewed when SPBRG is odd.
LS bit corruption during
transmission when SPBRG = 3.
Clock fails to stop at end of
character transmission when
SPBRG = 0.
FVRST bit activates prematurely. X
IVRST bit activates prematurely.
Unexpected BOR occurrence.
HFINTOSC output accuracy.
Unexpected code execution at
low V
Premature POR release.
POR may become stuck.
48 MHz maximum frequency.
Presetting interrupt-on-change
issue.
Endurance is limited to 10K
cycles.
Endurance is limited to 1K
cycles.
HFOFST bit erases to ‘0’ instead
of ‘1’.
DD
Issue Summary
.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
2010 Microchip Technology Inc.
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected Revisions
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X