PIC18F24K20-I/SP Microchip Technology, PIC18F24K20-I/SP Datasheet - Page 5
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PIC18F24K20-I/SP
Manufacturer Part Number
PIC18F24K20-I/SP
Description
IC PIC MCU FLASH 8KX16 28-DIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(12 pages)
3.PIC18F25K20T-ISS.pdf
(14 pages)
4.PIC18F25K20T-ISS.pdf
(456 pages)
5.PIC18F26K20-ISO.pdf
(430 pages)
Specifications of PIC18F24K20-I/SP
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
CCP/ECCP/EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
11-ch x 10-bit
Package
28SPDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
7. Module: MSSP I
8. Module: MSSP SPI
9. Module: MSSP SPI
10. Module: MSSP SPI
2010 Microchip Technology Inc.
I
Work around
Use software to emulate Master mode.
Affected Silicon Revisions
In SPI Master mode, when the CKE bit is cleared
and the SMP bit is set, the last bit of the incoming
data stream (bit 0) at the SDI pin will not be
sampled properly.
Work around
None.
Affected Silicon Revisions
In SPI Master mode, when CKE bit is set, the
SSPBUF will reload the SSPSR output shift
register on every high-to-low transition of the SS
pin.
Work around
Avoid using the SS pin when the CKE bit is set and
the MSSP is configured for SPI Master mode.
Affected Silicon Revisions
When SPI is enabled in Master mode with
CKE = 1 and CKP = 0, a 1/F
occur on the SCK pin.
Work around
Configure SCK pin as an input until after the MSSP
is setup.
Affected Silicon Revisions
2
C Master mode is not functional (Rev. A4 only).
X
X
X
X
X
X
X
X
X
X
X
X
2
X
X
X
X
C
PIC18F24K20/25K20/44K20/45K20
OSC
wide pulse will
11. Module: EUSART
12. Module: EUSART
13. Module: EUSART
In Synchronous Master mode, when the SPBRG is
set to an odd number, the duty cycle of the CK
output will be skewed by one baud clock count.
Work around
High values of SPBRG will minimize the effect of
this anomaly.
Affected Silicon Revisions
In Synchronous Master mode, when the SPBRG is
set to 3 and the TXREG is written while the
previous character is still in the TX shift register,
the LS bit of the TXREG character may be
corrupted during transmission.
Work around
When SPBRG is set to 3, wait until the TRMT bit of
the TXSTA register is set before loading TXREG
with the next character to be transmitted.
Affected Silicon Revisions
In Synchronous Master mode, if the SPBRG
register is equal to 0 when the TXEN bit is set, then
writing to TXREG will properly start transmission.
However, the clock will be improperly out of phase
with the data bits and the clock will not stop at the
end of the character transmission.
Work around
Set SPBRG register to non-zero value before
setting the TXEN bit.
Affected Silicon Revisions
X
X
X
X
X
X
X
X
X
X
X
X
DS80425G-page 5