PIC24F08KA101-I/MQ Microchip Technology, PIC24F08KA101-I/MQ Datasheet - Page 198
![IC PIC MCU FLASH 1KX8 20-QFN](/photos/6/98/69844/c04-139_mq_sml.jpg)
PIC24F08KA101-I/MQ
Manufacturer Part Number
PIC24F08KA101-I/MQ
Description
IC PIC MCU FLASH 1KX8 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA240017.pdf
(254 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F16KA101-ISS.pdf
(18 pages)
Specifications of PIC24F08KA101-I/MQ
Program Memory Type
FLASH
Program Memory Size
8KB (2.75K x 24)
Package / Case
20-VQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1.5 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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PIC24F16KA102 FAMILY
26.2
For the PIC24F16KA102 family of devices, the WDT is
driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (T
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the Configuration bits,
WDTPS<3:0> (FWDT<3:0>), which allow the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
• When a PWRSAV instruction is executed
• When the device exits Sleep or Idle mode to
• By a CLRWDT instruction during normal execution
If the WDT is enabled, it will continue to run during
Sleep or Idle modes. When the WDT time-out occurs,
the device will wake the device and code execution will
continue from where the PWRSAV instruction was
FIGURE 26-1:
DS39927B-page 196
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
(i.e., Sleep or Idle mode is entered)
resume normal operation
Sleep or Idle Mode
New Clock Source
All Device Resets
CLRWDT Instr.
PWRSAV Instr.
Exit Sleep or
Transition to
LPRC Input
Watchdog Timer (WDT)
SWDTEN
Idle Mode
FWDTEN
WDT BLOCK DIAGRAM
WDT
31 kHz
) of 1 ms in 5-bit mode or
(5-Bit/7-Bit)
Prescaler
FWPSA
1 ms/4 ms
LPRC Control
Preliminary
Counter
WDT
executed. The corresponding SLEEP or IDLE bits
(RCON<3:2>) will need to be cleared in software after
the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not
automatically cleared following a WDT time-out. To
detect subsequent WDT events, the flag must be
cleared in software.
26.2.1
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
Configuration bit, WINDIS (FWDT<6>), to ‘0’.
26.2.2
The WDT is enabled or disabled by the FWDTEN
Configuration bit. When the FWDTEN Configuration bit
is set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN Configuration bit has been programmed
to ‘0’. The WDT is enabled in software by setting the
SWDTEN control bit (RCON<5>). The SWDTEN
control bit is cleared on any device Reset. The software
WDT option allows the user to enable the WDT for
critical code segments and disable the WDT during
non-critical segments for maximum power savings.
Note:
1:1 to 1:32.768
WDTPS<3:0>
Postscaler
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
WINDOWED OPERATION
CONTROL REGISTER
© 2009 Microchip Technology Inc.
WDT Overflow
Wake from Sleep
Reset
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