PIC24F08KA101-I/MQ Microchip Technology, PIC24F08KA101-I/MQ Datasheet - Page 24
![IC PIC MCU FLASH 1KX8 20-QFN](/photos/6/98/69844/c04-139_mq_sml.jpg)
PIC24F08KA101-I/MQ
Manufacturer Part Number
PIC24F08KA101-I/MQ
Description
IC PIC MCU FLASH 1KX8 20-QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.MA240017.pdf
(254 pages)
2.PIC24F04KA201-ISS.pdf
(48 pages)
3.PIC24F16KA101-ISS.pdf
(18 pages)
Specifications of PIC24F08KA101-I/MQ
Program Memory Type
FLASH
Program Memory Size
8KB (2.75K x 24)
Package / Case
20-VQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Eeprom Size
512 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24F
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1.5 KB
Interface Type
I2C/IrDA/SPI/UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM240001
Minimum Operating Temperature
- 40 C
On-chip Adc
9-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
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PIC24F16KA102 FAMILY
3.2
REGISTER 3-1:
DS39927B-page 22
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0, HSC
IPL2
U-0
—
2:
CPU Control Registers
(2)
The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
(1)
Unimplemented: Read as ‘0’
DC: ALU Half Carry/Borrow bit
1 = A carry-out from the 4
0 = No carry-out from the 4
IPL<2:0>: CPU Interrupt Priority Level Status bits
111 = CPU interrupt priority level is 7 (15); user interrupts disabled
110 = CPU interrupt priority level is 6 (14)
101 = CPU Interrupt priority Level is 5 (13)
100 = CPU interrupt priority level is 4 (12)
011 = CPU interrupt priority level is 3 (11)
010 = CPU interrupt priority level is 2 (10)
001 = CPU interrupt priority level is 1 (9)
000 = CPU interrupt priority level is 0 (8)
RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
N: ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
Z: ALU Zero bit
1 = An operation, which effects the Z bit, has set it at some time in the past
0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)
C: ALU Carry/Borrow bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit (MSb) of the result occurred
R/W-0, HSC
IPL1
of the result occurred
SR: ALU STATUS REGISTER
U-0
—
(2)
(1)
HSC = Hardware Settable/Clearable bit
W = Writable bit
‘1’ = Bit is set
R/W-0, HSC
IPL0
U-0
—
(2)
th
th
low-order bit (for byte-sized data) or 8
(1)
or 8
R-0, HSC
Preliminary
th
low-order bit of the result has occurred
U-0
RA
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC
(1,2)
U-0
—
N
U-0
OV
—
th
low-order bit (for word-sized data)
© 2009 Microchip Technology Inc.
x = Bit is unknown
U-0
—
Z
R/W-0, HSC
DC
C
bit 8
bit 0
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