PIC18F44J10-I/P Microchip Technology, PIC18F44J10-I/P Datasheet - Page 142
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F44J10-I/P
Manufacturer Part Number
PIC18F44J10-I/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F24J10-ISO.pdf
(368 pages)
3.PIC18F24J10-ISO.pdf
(6 pages)
4.PIC18F24J10-ISO.pdf
(6 pages)
5.PIC18F24J10-ISO.pdf
(12 pages)
6.PIC18LF24J10-ISS.pdf
(32 pages)
7.PIC18F44J10-IPT.pdf
(358 pages)
Specifications of PIC18F44J10-I/P
Program Memory Type
FLASH
Program Memory Size
16KB (8K x 16)
Package / Case
40-DIP (0.600", 15.24mm)
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPIC/I2C/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DM183032, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164329 - MODULE SKT FOR 40DIP 18F45J10
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F44J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F44J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F44J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F24J10-ISO PDF datasheet #2
- PIC18F24J10-ISO PDF datasheet #3
- PIC18F24J10-ISO PDF datasheet #4
- PIC18F24J10-ISO PDF datasheet #5
- PIC18LF24J10-ISS PDF datasheet #6
- PIC18F44J10-IPT PDF datasheet #7
- Current page: 142 of 358
- Download datasheet (6Mb)
current from destroying the bridge power switches. The
illustration. Bits PDC6:PDC0 of the ECCP1DEL register
PIC18F45J10 FAMILY
14.4.6
In half-bridge applications, where all power switches
are modulated at the PWM frequency at all times, the
power switches normally require more time to turn off
than to turn on. If both the upper and lower power
switches are switched at the same time (one turned on
and the other turned off), both switches may be on for
a short period of time until one switch completely turns
off. During this brief interval, a very high current (shoot-
through current) may flow through both power
switches, shorting the bridge supply. To avoid this
potentially destructive shoot-through current from
flowing during switching, turning on either of the power
switches is normally delayed to allow the other switch
to completely turn off.
In the Half-Bridge Output mode, a digitally programmable
dead-band delay is available to avoid shoot-through
delay occurs at the signal transition from the nonactive
state to the active state. See Figure 14-4 for an
(Register 14-2) set the delay period in terms of microcon-
troller instruction cycles (T
not available in 28-pin devices as the standard CCP
module does not support half-bridge operation.
14.4.7
When the ECCP1 is programmed for any of the
Enhanced PWM modes, the active output pins may be
configured for auto-shutdown. Auto-shutdown immedi-
ately places the Enhanced PWM output pins into a
defined shutdown state when a shutdown event occurs.
REGISTER 14-2:
DS39682C-page 140
Note:
bit 7
bit 6-0
PROGRAMMABLE DEAD-BAND
DELAY
Programmable dead-band delay is not
implemented in 28-pin devices with
standard CCP modules.
ENHANCED PWM AUTO-SHUTDOWN
ECCP1DEL: PWM DEAD-BAND DELAY REGISTER
bit 7
PRSEN: PWM Restart Enable bit
1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event
0 = Upon auto-shutdown, ECCPASE must be cleared in software to restart the PWM
PDC6:PDC0: PWM Delay Count bits
Delay time, in number of F
a PWM signal to transition to active.
Legend:
R = Readable bit
-n = Value at POR
PRSEN
CY
R/W-0
Note 1: Reserved on 28-pin devices; maintain these bits clear.
goes away; the PWM restarts automatically
or 4 T
OSC
PDC6
R/W-0
). These bits are
(1)
PDC5
R/W-0
OSC
Preliminary
W = Writable bit
‘1’ = Bit is set
/4 (4 * T
(1)
PDC4
(1)
R/W-0
OSC
A shutdown event can be caused by either of the
comparator modules, a low level on the Fault input pin
(FLT0) or any combination of these three sources. The
comparators may be used to monitor a voltage input
proportional to a current being monitored in the bridge
circuit. If the voltage exceeds a threshold, the
comparator switches state and triggers a shutdown.
Alternatively, a low digital signal on FLT0 can also trigger
a shutdown. The auto-shutdown feature can be disabled
by not selecting any auto-shutdown sources. The auto-
shutdown sources to be used are selected using the
ECCPAS2:ECCPAS0 bits (bits<6:4> of the ECCP1AS
register).
When a shutdown occurs, the output pins are
asynchronously placed in their shutdown states, spec-
ified by the PSSAC1:PSSAC0 and PSSBD1:PSSBD0
bits (ECCPAS3:ECCPAS0). Each pin pair (P1A/P1C
and P1B/P1D) may be set to drive high, drive low or be
tri-stated
(ECCP1AS<7>) is also set to hold the Enhanced PWM
outputs in their shutdown states.
The ECCPASE bit is set by hardware when a shutdown
event occurs. If automatic restarts are not enabled, the
ECCPASE bit is cleared by firmware when the cause of
the shutdown clears. If automatic restarts are enabled,
the ECCPASE bit is automatically cleared when the
cause of the auto-shutdown has cleared.
If the ECCPASE bit is set when a PWM period begins,
the PWM outputs remain in their shutdown state for that
entire PWM period. When the ECCPASE bit is cleared,
the PWM outputs will return to normal operation at the
beginning of the next PWM period.
) cycles, between the scheduled and actual time for
Note:
(1)
PDC3
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
Writing to the ECCPASE bit is disabled
while a shutdown condition is active.
(not
(1)
driving).
PDC2
R/W-0
© 2007 Microchip Technology Inc.
(1)
The
x = Bit is unknown
PDC1
R/W-0
ECCPASE
(1)
PDC0
R/W-0
bit 0
(1)
bit
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