PIC18F6585-I/L Microchip Technology, PIC18F6585-I/L Datasheet
PIC18F6585-I/L
Specifications of PIC18F6585-I/L
Related parts for PIC18F6585-I/L
PIC18F6585-I/L Summary of contents
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... PIC18F6585/8585/6680/8680 Microcontrollers with ECAN Module 2004 Microchip Technology Inc. 64/68/80-Pin High-Performance, 64-Kbyte Enhanced Flash Data Sheet DS30491C ...
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... ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP service mark of Microchip Technology Incorporated in the U.S.A. ...
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... Enhanced Addressable USART module: - Supports RS-232, RS-485 and LIN 1.2 - Programmable wake-up on Start bit - Auto-baud detect • Parallel Slave Port (PSP) module 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Analog Features: • 16-channel, 10-bit Analog-to-Digital Converter module (A/D) with: - Fast sampling rate - Programmable acquisition time - Conversion available during Sleep • ...
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... Low-power, high-speed Flash technology • Fully static design • Wide operating voltage range (2.0V to 5.5V) • Industrial and Extended temperature ranges Program Memory Data Memory Device # Single-Word SRAM Bytes Instructions (bytes) PIC18F6585 48K 24576 3328 PIC18F6680 64K 32768 3328 PIC18F8585 48K 24576 3328 ...
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... RE1/WR 1 RE0/RD 2 RG0/CANTX1 3 RG1/CANTX2 4 RG2/CANRX 5 RG3 6 RG5/MCLR RG4/P1D RF7/SS 11 RF6/AN11/C1IN- 12 RF5/AN10/C1IN+/CV REF 13 RF4/AN9/C2IN- 14 RF3/AN8/C2IN+ 15 RF2/AN7/C1OUT 16 Note 1: CCP2 pin placement depends on CCP2MX setting. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 PIC18F6X8X RB0/INT0 48 RB1/INT1 47 RB2/INT2 46 RB3/INT3 45 RB4/KBI0 44 RB5/KBI1/PGM 43 RB6/KBI2/PGC OSC2/CLKO/RA6 40 OSC1/CLKI RB7/KBI3/PGD 37 RC5/SDO 36 RC4/SDI/SDA ...
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... PIC18F6585/8585/6680/8680 Pin Diagrams (Continued) 68-Pin PLCC 10 RE1/WR 11 RE0/RD 12 RG0/CANTX1 13 RG1/CANTX2 14 RG2/CANRX 15 RG3 16 RG5/MCLR RG4/P1D 18 N RF7/SS RF6/AN11/C1IN RF5/AN10/C1IN+/CV REF RF4/AN9/C2IN- 24 RF3/AN8/C2IN RF2/AN7/C1OUT Note 1: CCP2 pin placement depends on CCP2MX setting. DS30491C-page Top View PIC18F6X8X RB0/INT0 59 RB1/INT1 58 RB2/INT2 57 RB3/INT3 56 RB4/KBI0 55 RB5/KBI1/PGM 54 RB6/KBI2/PGC N/C ...
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... RF3/AN8/C2IN+ 17 RF2/AN7/C1OUT 18 (3) RH7/AN15/P1B 19 (3) RH6/AN14/P1C Note 1: PSP is available only in Microcontroller mode. 2: CCP2 pin placement depends on CCP2MX and Processor mode settings. 3: P1B and P1C pin placement depends on ECCPMX setting. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 PIC18F8X8X RJ2/WRL 60 RJ3/WRH 59 RB0/INT0 58 RB1/INT1 57 RB2/INT2 ...
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... Appendix C: Conversion Considerations ........................................................................................................................................... 470 Appendix D: Migration from Mid-Range to Enhanced Devices .......................................................................................................... 470 Appendix E: Migration from High-End to Enhanced Devices............................................................................................................. 471 Index .................................................................................................................................................................................................. 473 On-Line Support................................................................................................................................................................................. 487 Systems Information and Upgrade Hot Line ...................................................................................................................................... 487 Reader Response .............................................................................................................................................................................. 488 PIC18F6585/8585/6680/8680 Product Identification System ............................................................................................................ 489 DS30491C-page 6 2004 Microchip Technology Inc. ...
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... When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter- ature number) you are using. Customer Notification System Register on our Web site at www.microchip.com/cn to receive the most current information on all of our products. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 DS30491C-page 7 ...
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... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 8 2004 Microchip Technology Inc. ...
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... PSP is only available in Microcontroller mode. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 All other PIC18F6585/8585/6680/8680 family are identical. These are summarized in Table 1-1. Block diagrams of the PIC18F6X8X and PIC18F8X8X devices are provided in Figure 1-1 and Figure 1-2, respectively. The pinouts for these device families are listed in Table 1-2 ...
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... PIC18F6585/8585/6680/8680 FIGURE 1-1: PIC18F6X8X BLOCK DIAGRAM Table Pointer<21> 21 inc/dec logic 21 21 PCLATU PCU Program Counter Address Latch Program Memory 31 Level Stack (48 Kbytes) Data Latch Table Latch 8 16 ROM Latch Instruction Decode & Control Power-up OSC2/CLKO/RA6 OSC1/CLKI Timing Oscillator Generation Start-up Timer ...
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... CCP2 Comparator AUSART Note 1: The CCP2 pin placement depends on the CCP2MX and Processor mode settings. 2: P1B and P1C pin placement depends on the ECCPMX setting. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Data Bus<8> Data Latch 8 8 Data RAM (3328 bytes) Address Latch ...
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... PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RG5/MCLR RG5 MCLR V PP OSC1/CLKI 39 50 OSC1 CLKI OSC2/CLKO/RA6 40 51 OSC2 CLKO RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power Note 1: Alternate assignment for CCP2 in all operating modes except Microcontroller – ...
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... TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RA0/AN0 24 34 RA0 AN0 RA1/AN1 23 33 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 39 RA4 T0CKI RA5/AN4/LVDIN 27 38 RA5 AN4 ...
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... PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RB0/INT0 48 60 RB0 INT0 RB1/INT1 47 59 RB1 INT1 RB2/INT2 46 58 RB2 INT2 RB3/INT3/CCP2 45 57 RB3 INT3 (1) CCP2 RB4/KBI0 44 56 RB4 KBI0 RB5/KBI1/PGM 43 55 RB5 KBI1 ...
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... TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RC0/T1OSO/T13CKI 30 41 RC0 T1OSO T13CKI RC1/T1OSI/CCP2 29 40 RC1 T1OSI (1, 4) CCP2 RC2/CCP1/P1A 33 44 RC2 CCP1 P1A RC3/SCK/SCL 34 45 RC3 SCK SCL RC4/SDI/SDA 35 46 RC4 SDI SDA ...
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... PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RD0/PSP0/AD0 58 3 RD0 (6) PSP0 (3) AD0 RD1/PSP1/AD1 55 67 RD1 (6) PSP1 (3) AD1 RD2/PSP2/AD2 54 66 RD2 (6) PSP2 (3) AD2 RD3/PSP3/AD3 53 65 RD3 (6) PSP3 (3) AD3 RD4/PSP4/AD4 52 64 RD4 (6) PSP4 (3) AD4 ...
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... TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RE0/RD/AD8 2 11 RE0 (6) RD (3) AD8 RE1/WR/AD9 1 10 RE1 (6) WR (3) AD9 RE2/CS/AD10 64 RE2 (6) CS (3) AD10 RE3/AD11 63 RE3 (3) AD11 RE4/AD12 62 RE4 (3) AD12 RE5/AD13/P1C 61 RE5 (3) AD13 (7) P1C RE6/AD14/P1B 60 RE6 ...
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... PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RF0/AN5 18 28 RF0 AN5 RF1/AN6/C2OUT 17 27 RF1 AN6 C2OUT RF2/AN7/C1OUT 16 26 RF2 AN7 C1OUT RF3/AN8/C2IN RF1 AN8 C2IN+ RF4/AN9/C2IN RF1 AN9 C2IN- RF5/AN10/C1IN+/ REF RF1 ...
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... TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RG0/CANTX1 3 12 RG0 CANTX1 RG1/CANTX2 4 13 RG1 CANTX2 RG2/CANRX 5 14 RG2 CANRX RG3 6 15 RG3 RG4/P1D 8 17 RG4 P1D RG5 7 16 Legend: TTL = TTL compatible input ...
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... PIC18F6585/8585/6680/8680 TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RH0/A16 — — RH0 A16 RH1/A17 — — RH1 A17 RH2/A18 — — RH2 A18 RH3/A19 — — RH3 A19 RH4/AN12 — — RH4 AN12 RH5/AN13 — ...
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... TABLE 1-2: PIC18F6585/8585/6680/8680 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18F6X8X PIC18F8X8X TQFP PLCC RJ0/ALE — — RJ0 ALE RJ1/OE — — RJ1 OE RJ2/WRL — — RJ2 WRL RJ3/WRH — — RJ3 WRH RJ4/BA0 — — RJ4 BA0 RJ5/CE — ...
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... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 22 2004 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F6585/8585/6680/8680 devices can be operated in eleven different oscillator modes. The user can program four configuration bits (FOSC3, FOSC2, FOSC1 and FOSC0) to select one of these eleven modes Low-Power Crystal 2. XT Crystal/Resonator 3. HS High-Speed Crystal/Resonator 4. RC External Resistor/Capacitor 5 ...
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... PIC18F6585/8585/6680/8680 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Ranges Tested: Mode Freq C1 LP 32.0 kHz 33 pF 200 kHz 200 kHz 47-68 pF 1.0 MHz 15 pF 4.0 MHz 4.0 MHz 15 pF 8.0 MHz 15-33 pF 20.0 MHz 15-33 pF 25.0 MHz TBD These values are for design guidance only. ...
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... OSC1. There are two types of PLL modes: Software Controlled PLL and Configuration bits Controlled PLL. In Software Controlled PLL mode, PIC18F6585/8585/6680/8680 executes at regular clock frequency after all Reset conditions. During execution, application can enable PLL and switch to 4x clock frequency operation by setting the PLLEN bit in the OSCCON register ...
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... PIC18F6585/8585/6680/8680 2.6 Oscillator Switching Feature The PIC18F6585/8585/6680/8680 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low-frequency clock source. PIC18F6585/8585/6680/8680 devices, this alternate clock source is the Timer1 oscillator low-frequency crystal (32 kHz, for example) has been attached to the ...
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... The setting of SCS0 = 1 supersedes SCS1 = 1. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 enabled (PLLEN = 1) and locked (LOCK = 1), else it will be forced clear. When programmed with Configuration Controlled PLL mode, the SCS1 bit will be forced clear. Note: The Timer1 oscillator must be enabled and operating to switch the system clock source ...
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... PIC18F6585/8585/6680/8680 2.6.2 OSCILLATOR TRANSITIONS PIC18F6585/8585/6680/8680 devices contain circuitry to prevent “glitches” when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switch- ing to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources ...
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... Clock SCS (OSCCON<0>) Program Counter PC 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 If the main oscillator is configured for EC mode with PLL ) plus an active, only the PLL time-out (T OST time-out is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram, indicat- ing the transition from the Timer1 oscillator to the main oscillator for EC with PLL active, is shown in Figure 2-11 ...
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... PIC18F6585/8585/6680/8680 If the main oscillator is configured in the RC, RCIO ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram, indi- cating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes, is shown in Figure 2-12 ...
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... Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 switching currents have been removed, Sleep mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during Sleep will increase the current consumed during Sleep ...
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... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 32 2004 Microchip Technology Inc. ...
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... RESET The PIC18F6585/8585/6680/8680 devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during Sleep d) Watchdog Timer (WDT) Reset (during normal operation) e) Programmable Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset Most registers are unaffected by a Reset ...
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... PIC18F6585/8585/6680/8680 3.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when V rise is detected. To take advantage of the POR cir- DD cuitry, tie the MCLR pin through tor This will eliminate external RC components DD usually needed to create a Power-on Reset delay. A minimum rise rate for V is specified (parameter DD D004) ...
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... Legend unchanged unknown, – = unimplemented bit, read as ‘0’ Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (000008h or 000018h). 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 (2) Power-up PWRTE = 1 + 2ms ...
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... PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices TOSU PIC18F6X8X PIC18F8X8X TOSH PIC18F6X8X PIC18F8X8X TOSL PIC18F6X8X PIC18F8X8X STKPTR PIC18F6X8X PIC18F8X8X PCLATU PIC18F6X8X PIC18F8X8X PCLATH PIC18F6X8X PIC18F8X8X PCL PIC18F6X8X PIC18F8X8X TBLPTRU PIC18F6X8X PIC18F8X8X TBLPTRH PIC18F6X8X PIC18F8X8X TBLPTRL PIC18F6X8X PIC18F8X8X ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices ADRESH PIC18F6X8X PIC18F8X8X ADRESL PIC18F6X8X PIC18F8X8X ADCON0 PIC18F6X8X PIC18F8X8X ADCON1 PIC18F6X8X PIC18F8X8X ADCON2 PIC18F6X8X PIC18F8X8X CCPR1H PIC18F6X8X PIC18F8X8X CCPR1L PIC18F6X8X PIC18F8X8X CCP1CON PIC18F6X8X PIC18F8X8X CCPR2H PIC18F6X8X PIC18F8X8X CCPR2L PIC18F6X8X PIC18F8X8X ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices PORTJ PIC18F6X8X PIC18F8X8X PORTH PIC18F6X8X PIC18F8X8X PORTG PIC18F6X8X PIC18F8X8X PORTF PIC18F6X8X PIC18F8X8X PORTE PIC18F6X8X PIC18F8X8X PORTD PIC18F6X8X PIC18F8X8X PORTC PIC18F6X8X PIC18F8X8X PORTB PIC18F6X8X PIC18F8X8X (5,6) PORTA PIC18F6X8X PIC18F8X8X SPBRGH ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices TXB0SIDH PIC18F6X8X PIC18F8X8X TXB0CON PIC18F6X8X PIC18F8X8X TXB1D7 PIC18F6X8X PIC18F8X8X TXB1D6 PIC18F6X8X PIC18F8X8X TXB1D5 PIC18F6X8X PIC18F8X8X TXB1D4 PIC18F6X8X PIC18F8X8X TXB1D3 PIC18F6X8X PIC18F8X8X TXB1D2 PIC18F6X8X PIC18F8X8X TXB1D1 PIC18F6X8X PIC18F8X8X TXB1D0 PIC18F6X8X PIC18F8X8X ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices (7) B5D7 PIC18F6X8X PIC18F8X8X (7) B5D6 PIC18F6X8X PIC18F8X8X (7) B5D5 PIC18F6X8X PIC18F8X8X (7) B5D4 PIC18F6X8X PIC18F8X8X (7) B5D3 PIC18F6X8X PIC18F8X8X (7) B5D2 PIC18F6X8X PIC18F8X8X (7) B5D1 PIC18F6X8X PIC18F8X8X (7) B5D0 PIC18F6X8X PIC18F8X8X (7) B5DLC PIC18F6X8X PIC18F8X8X (7) B5EIDL PIC18F6X8X PIC18F8X8X ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices (7) B1D1 PIC18F6X8X PIC18F8X8X (7) B1D0 PIC18F6X8X PIC18F8X8X (7) B1DLC PIC18F6X8X PIC18F8X8X (7) B1EIDL PIC18F6X8X PIC18F8X8X (7) B1EIDH PIC18F6X8X PIC18F8X8X (7) B1SIDL PIC18F6X8X PIC18F8X8X (7) B1SIDH PIC18F6X8X PIC18F8X8X (7) B1CON PIC18F6X8X PIC18F8X8X (7) B0D7 PIC18F6X8X PIC18F8X8X (7) B0D6 PIC18F6X8X PIC18F8X8X ...
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... Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they read ‘0’. 7: This register reads all ‘0’s until ECAN is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 MCLR Resets Power-on Reset, WDT Reset ...
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... PIC18F6585/8585/6680/8680 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices (7) RXF10SIDL PIC18F6X8X PIC18F8X8X (7) RXF10SIDH PIC18F6X8X PIC18F8X8X (7) RXF9EIDL PIC18F6X8X PIC18F8X8X (7) RXF9EIDH PIC18F6X8X PIC18F8X8X (7) RXF9SIDL PIC18F6X8X PIC18F8X8X (7) RXF9SIDH PIC18F6X8X PIC18F8X8X (7) RXF8EIDL PIC18F6X8X PIC18F8X8X (7) RXF8EIDH PIC18F6X8X PIC18F8X8X (7) RXF8SIDL PIC18F6X8X PIC18F8X8X (7) RXF8SIDH PIC18F6X8X PIC18F8X8X ...
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... INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 T PWRT T OST T PWRT T T PWRT T VIA 1 k RESISTOR CASE 1 DD ...
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... PIC18F6585/8585/6680/8680 FIGURE 3-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED MCLR IINTERNAL POR PWRT TIME-OUT OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note 1024 clock cycles. ...
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... The Reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. Figure 4-1 shows the program memory map for PIC18F6585/8585 devices while Figure 4-2 shows the program memory map for PIC18F6680/8680 devices. 2004 Microchip Technology Inc. ...
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... PIC18F6585/8585/6680/8680 FIGURE 4-1: INTERNAL PROGRAM MEMORY MAP AND STACK FOR PIC18F6585/8585 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 31 000000h Reset Vector High Priority Interrupt Vector 000008h Low Priority Interrupt Vector 000018h On-Chip Flash Program Memory 00BFFFh 00C000h Read ‘0’ 1FFFFFh ...
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... External Program Memory 1FFFFFh 1FFFFFh External On-Chip Memory Flash Note 1: PIC18F6585 and PIC18F8585. 2: PIC18F6680 and PIC18F8680. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 U-0 U-0 U-0 — — — — Programmable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
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... PIC18F6585/8585/6680/8680 4.2 Return Address Stack The return address stack allows any combination program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW RETFIE instruction. PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions ...
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... POP instruction. The POP instruc- tion discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 R/W-0 R/W-0 (1) — ...
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... PIC18F6585/8585/6680/8680 4.3 Fast Register Stack A “fast interrupt return” option is available for interrupts. A fast register stack is provided for the Status, WREG and BSR registers and is only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt ...
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... Instruction 2: GOTO Instruction 3: MOVFF 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles ...
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... PIC18F6585/8585/6680/8680 4.7.1 TWO-WORD INSTRUCTIONS The PIC18F6585/8585/6680/8680 devices have four two-word instructions: MOVFF, CALL, LFSR. The second word of these instructions has the 4 MSBs set to ‘1’s and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruc- ...
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... Figure 4-7 shows the data memory organization for the PIC18F6585/8585/6680/8680 devices. The data memory map is divided into 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR< ...
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... PIC18F6585/8585/6680/8680 FIGURE 4-7: DATA MEMORY MAP FOR PIC18FXX80/XX85 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh = 0100 Bank 4 Bank 5 to Bank 12 = 1101 Bank 13 00h = 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh ...
Page 63
... FE2h FSR1H FC2h FE1h FSR1L FC1h FE0h BSR FC0h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Name Address Name (3) INDF2 FBFh CCPR1H (3) POSTINC2 FBEh CCPR1L (3) ...
Page 64
... PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address F7Fh SPBRGH F5Fh F7Eh BAUDCON F5Eh CANSTAT_RO0 (1) F7Dh — F5Dh (1) F7Ch — F5Ch (1) F7Bh — F5Bh (1) F7Ah — F5Ah F79h ECCP1DEL F59h (1) F78h — F58h F77h ECANCON F57h F76h TXERRCNT ...
Page 65
... EC2h (1) EE1h — EC1h (1) EE0h — EC0h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Name Address Name (1) (1) — EBFh — (1) (1) — EBEh — ...
Page 66
... PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address E7Fh CANCON_RO4 E5Fh E7Eh CANSTAT_RO4 E5Eh CANSTAT_RO6 E7Dh B5D7 E5Dh E7Ch B5D6 E5Ch E7Bh B5D5 E5Bh E7Ah B5D4 E5Ah E79h B5D3 E59h E78h B5D2 E58h E77h B5D1 E57h E76h B5D0 ...
Page 67
... RXFBCON2 DC2h DE1h RXFBCON1 DC1h DE0h RXFBCON0 DC0h Note 1: Unimplemented registers are read as ‘0’. 2: This register is not available on PIC18F6X8X devices. 3: This is not a physical register. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Name Address Name (1) (1) — DBFh — (1) (1) — DBEh — ...
Page 68
... PIC18F6585/8585/6680/8680 TABLE 4-2: SPECIAL FUNCTION REGISTER MAP (CONTINUED) Address Name Address (1) D7Fh — (1) D7Eh — (1) D7Dh — (1) D7Ch — D7Bh RXF11EIDL D7Ah RXF11EIDH D79h RXF11SIDL D78h RXF11SIDH D77h RXF10EIDL D76h RXF10EIDH D75h RXF10SIDL D74h RXF10SIDH D73h RXF9EIDL D72h RXF9EIDH D71h RXF9SIDL ...
Page 69
... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 Bit 2 — ...
Page 70
... PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 STATUS — — TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT OSCCON — — LVDCON — — WDTCON — — RCON IPEN — TMR1H Timer1 Register High Byte ...
Page 71
... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 Bit 2 TXEN ...
Page 72
... PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 (3) PORTJ Read PORTJ pins, Write PORTJ Data Latch (3) PORTH Read PORTH pins, Write PORTH Data Latch PORTG — — PORTF Read PORTF pins, Write PORTF Data Latch PORTE Read PORTE pins, Write PORTE Data Latch ...
Page 73
... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 Bit 2 RB1 ...
Page 74
... PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 TXB1D7 TXB1D77 TXB1D76 TXB1D75 TXB1D6 TXB1D67 TXB1D66 TXB1D65 TXB1D5 TXB1D57 TXB1D56 TXB1D55 TXB1D4 TXB1D47 TXB1D46 TXB1D45 TXB1D3 TXB1D37 TXB1D36 TXB1D35 TXB1D2 TXB1D27 TXB1D26 TXB1D25 TXB1D1 TXB1D17 TXB1D16 TXB1D15 TXB1D0 TXB1D07 ...
Page 75
... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 Bit 2 EID13 ...
Page 76
... PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 RXF5SIDL SID2 SID1 RXF5SIDH SID10 SID9 RXF4EIDL EID7 EID6 RXF4EIDH EID15 EID14 RXF4SIDL SID2 SID1 RXF4SIDH SID10 SID9 RXF3EIDL EID7 EID6 RXF3EIDH EID15 EID14 RXF3SIDL SID2 SID1 RXF3SIDH SID10 SID9 ...
Page 77
... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 Bit 2 B4D35 ...
Page 78
... PIC18F6585/8585/6680/8680 TABLE 4-3: REGISTER FILE SUMMARY (CONTINUED) File Name Bit 7 Bit 6 (5, 7) B2CON RXFUL/ RXM1/ RTRRO/ TXBIF TXABT TXLARB (7) B1D7 B1D77 B1D76 (7) B1D6 B1D67 B1D66 (7) B1D5 B1D57 B1D56 (7) B1D4 B1D47 B1D46 (7) B1D3 B1D37 B1D36 (7) B1D2 B1D27 B1D26 (7) B1D1 B1D17 B1D16 (7) B1D0 ...
Page 79
... Meaning of this register depends on whether this buffer is configured as transmit or receive. 6: RG5 is available as an input when MCLR is disabled. 7: This register reads all ‘0’s until the ECAN module is set up in Mode 1 or Mode 2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 5 Bit 4 Bit 3 Bit 2 F15BP_0 ...
Page 80
... PIC18F6585/8585/6680/8680 4.10 Access Bank The Access Bank is an architectural enhancement which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. This data memory region can be used for: • Intermediate computational values • Local variables of subroutines • ...
Page 81
... FSR register being the address of the data instruction writes a value to INDF0, the value will be written to the address pointed to by FSR0H:FSR0L. A read from INDF1 reads 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 the data from FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used ...
Page 82
... PIC18F6585/8585/6680/8680 If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions. FIGURE 4-9: INDIRECT ADDRESSING OPERATION Instruction Executed Opcode BSR<3:0> Instruction Fetched Opcode FIGURE 4-10: INDIRECT ADDRESSING 11 Location Select Note 1: For register file map detail, see Table 4-2 ...
Page 83
... Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the Status register as 000u u1uu (where u = unchanged recommended, therefore, that only BCF, BSF, ...
Page 84
... PIC18F6585/8585/6680/8680 4.14 RCON Register The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device Reset. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 4-4: RCON REGISTER R/W-0 IPEN ...
Page 85
... TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 5.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes DD between the program memory space and the data RAM: • ...
Page 86
... PIC18F6585/8585/6680/8680 FIGURE 5-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of eight holding registers, the address of which is determined by TBLPTRL<2:0>. The process for physically writing data to the program memory array is discussed in Section 5.5 “Writing to Flash Program Memory”. ...
Page 87
... RD bit cannot be set when EEPGD = 1 Does not initiate an EEPROM read Legend Readable bit W = Writable bit ‘1’ = Bit is set 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 R/W-0 R/W-x — FREE WRERR U = Unimplemented bit, read as ‘0’ ...
Page 88
... PIC18F6585/8585/6680/8680 5.2.2 TABLAT – TABLE LATCH REGISTER The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch is used to hold 8- bit data during data transfers between program memory and data RAM. 5.2.3 TBLPTR – TABLE POINTER REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory ...
Page 89
... MOVF TABLAT, W MOVWF MSB 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
Page 90
... PIC18F6585/8585/6680/8680 5.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer or through ICSP control can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 64 bytes of program memory is erased ...
Page 91
... TBLPTR = xxxxx0 TBLPTR = xxxxx1 Holding Register 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 the holding registers are written. At the end of updating eight registers, the EECON1 register must be written to, to start the programming operation with a long write. The long write is necessary for programming the inter- nal Flash ...
Page 92
... PIC18F6585/8585/6680/8680 5.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. Read 64 bytes into RAM. 2. Update data values in RAM as necessary. 3. Load table pointer with address being erased the row erase procedure. 5. Load table pointer with address of first byte being written ...
Page 93
... INTCON, GIE DECFSZ COUNTER_HI BRA PROGRAM_LOOP BCF EECON1, WREN 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 ; load TBLPTR with the base ; address of the memory block ; point to Flash program memory ; access Flash program memory ; enable write to memory ; enable Row Erase operation ; disable interrupts ...
Page 94
... PIC18F6585/8585/6680/8680 5.5.2 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 5.5.3 UNEXPECTED TERMINATION OF ...
Page 95
... Section 4.1.1 “PIC18F8X8X Program Modes”. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 6.1 Program Memory Modes and the External Memory Interface As previously noted, PIC18F8X8X controllers are capable of operating in any one of four program mem- ory modes using combinations of on-chip and external program memory ...
Page 96
... PIC18F6585/8585/6680/8680 REGISTER 6-1: MEMCON REGISTER R/W-0 (1) EBDIS bit 7 bit 7 EBDIS: External Bus Disable bit 1 = External system bus disabled, all external bus drivers are mapped as I/O ports 0 = External system bus enabled and I/O ports are disabled Note 1: This bit is ignored when device is accessing external memory either to fetch an instruction or perform TBLRD/TBLWT ...
Page 97
... RJ7/UB PORTJ bit 7 Input/Output or System Bus Upper Byte Enable (UB) Control pin 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 When the device is executing out of internal memory (with EBDIS = 0) in Microprocessor with Boot Block mode or Extended Microcontroller mode, the control sig- nals will be in inactive. They will state where the AD< ...
Page 98
... PIC18F6585/8585/6680/8680 6.2 16-bit Mode The external memory interface implemented in PIC18F8X8X devices operates only in 16-bit mode. The mode selection is not software configurable but is programmed via the configuration bits. The WM<1:0> bits in the MEMCON register determine three types of connections in 16-bit mode. They are referred to as: • ...
Page 99
... WORD WRITE MODE EXAMPLE PIC18F8X8X AD<7:0> AD<15:8> ALE A<19:16> WRH Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 A<20:1> 373 D<15:0> 373 JEDEC Word A<x:0> EPROM Memory D<15:0> (1) CE ...
Page 100
... PIC18F6585/8585/6680/8680 6.2.3 16-BIT BYTE SELECT MODE Figure 6-3 shows an example of 16-bit Byte Select mode for PIC18F8X8X devices. FIGURE 6-3: 16-BIT BYTE SELECT MODE EXAMPLE PIC18F8X8X AD<7:0> AD<15:8> ALE A<19:16> OE WRH WRL BA0 Note 1: This signal only applies to table writes. See Section 5.1 “Table Reads and Table Writes”. ...
Page 101
... FIGURE 6-4: EXTERNAL PROGRAM MEMORY BUS TIMING (16-BIT MODE Apparent Q Actual A<19:16> 0h 3AABh AD<15:0> BA0 ALE OE WRH ‘1’ WRL ‘1’ Opcode Fetch MOVLW 55h from 007556h 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 0E55h CF33h Table Read of 92h from 199E67h 9256h ‘ ...
Page 102
... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 100 2004 Microchip Technology Inc. ...
Page 103
... Please refer to parameter D122 (Electrical Characteristics, Section 27.0 “Electrical Characteristics”) for exact limits. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 7.1 EEADRH:EEADR The address register pair, EEADRH:EEADR, can address maximum of 1024 bytes of data EEPROM ...
Page 104
... PIC18F6585/8585/6680/8680 REGISTER 7-1: EECON1 REGISTER (ADDRESS FA6h) R/W-x R/W-x EEPGD CFGS bit 7 bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory bit 6 CFGS: Flash Program/Data EE or Configuration Select bit 1 = Access configuration or calibration registers ...
Page 105
... BCF EECON1, WREN 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 (EECON1<6>) (EECON1<0>). The data is available for the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation or until it is written to by the user (during a write operation). ...
Page 106
... PIC18F6585/8585/6680/8680 7.5 Write Verify Depending on the application, good programming practice may dictate that the value written to the mem- ory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. 7.6 Protection Against Spurious Write There are conditions when the device may not want to write to the data EEPROM memory ...
Page 107
... PIR2 — CMIF — PIE2 — CMIE — Legend unknown unchanged reserved, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Bit 4 Bit 3 Bit 2 Bit 1 INTE RBIE T0IF INTF — — ...
Page 108
... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 106 2004 Microchip Technology Inc. ...
Page 109
... HARDWARE MULTIPLIER 8.1 Introduction hardware multiplier is included in the ALU of the PIC18F6585/8585/6680/8680 devices. By making the multiply a hardware operation, it completes in a sin- gle instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored in the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the ALUSTA register ...
Page 110
... PIC18F6585/8585/6680/8680 Example 8-3 shows the sequence unsigned multiply. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers, RES3:RES0. EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 216) + (ARG1H ARG2L 28) + (ARG1L ARG2H 28) + (ARG1L ARG2L) EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE ...
Page 111
... INTERRUPTS The PIC18F6585/8585/6680/8680 devices have multi- ple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high or a low priority level. The high priority interrupt vector is at 000008h while the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress ...
Page 112
... PIC18F6585/8585/6680/8680 FIGURE 9-1: INTERRUPT LOGIC Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit ...
Page 113
... Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt ...
Page 114
... PIC18F6585/8585/6680/8680 REGISTER 9-2: INTCON2 REGISTER R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge ...
Page 115
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W-0 INT3IE ...
Page 116
... PIC18F6585/8585/6680/8680 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Flag registers (PIR1, PIR2 and PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 117
... A TMR1 or TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 R/W-0 R/W-0 — EEIF BCLIF W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 118
... PIC18F6585/8585/6680/8680 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 IRXIF WAKIF bit 7 bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit invalid message has occurred on the CAN bus invalid message on CAN bus bit 6 WAKIF: CAN bus Activity Wake-up Interrupt Flag bit ...
Page 119
... Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W-0 ADIE RCIE TXIE SSPIE W = Writable bit U = Unimplemented bit, read as ‘ ...
Page 120
... PIC18F6585/8585/6680/8680 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 U-0 R/W-0 — CMIE bit 7 bit 7 Unimplemented: Read as ‘0’ bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 EEIE: Data EEPROM/Flash Write Operation Interrupt Enable bit ...
Page 121
... FIFOWMIE: FIFO Watermark Interrupt Enable bit 1 = Enable FIFO watermark interrupt 0 = Disable FIFO watermark interrupt Note 1: In CAN Mode 1 and 2, this bit is forced to ‘0’. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W-0 R/W-0 (1) ERRIE TXB2IE/ ...
Page 122
... PIC18F6585/8585/6680/8680 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2 and IPR3). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 123
... High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 R/W-1 R/W-1 — EEIP BCLIP W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘ ...
Page 124
... PIC18F6585/8585/6680/8680 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 IRXIP WAKIP bit 7 bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 WAKIP: CAN bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 ERRIP: CAN bus Error Interrupt Priority bit ...
Page 125
... POR: Power-on Reset Status bit For details of bit operation, see Register 4-4. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-4. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘ ...
Page 126
... PIC18F6585/8585/6680/8680 9.6 INT0 Interrupt External interrupts on the RB0/INT0, RB1/INT1, RB2/ INT2 and RB3/INT3 pins are edge-triggered: either ris- ing if the corresponding INTEDGx bit is set in the INTCON2 register, or falling if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE ...
Page 127
... WR LAT + WR Port CK Data Latch Data Bus RD Port 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 10.1 PORTA, TRISA and LATA Registers PORTA is a 7-bit wide, bidirectional port. The corre- sponding data direction register is TRISA. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i ...
Page 128
... PIC18F6585/8585/6680/8680 FIGURE 10-2: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS RD LATA Data Bus LATA or PORTA Q CK Data Latch TRISA Q CK Analog TRIS Latch Input Mode RD TRISA PORTA To A/D Converter and LVD Modules Note 1: I/O pins have protection diodes to V FIGURE 10-4: BLOCK DIAGRAM OF RA6 PIN (WHEN ENABLED AS I/O) ...
Page 129
... VCFG1 VCFG0 PCFG3 Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function Input/output or analog input. Input/output or analog input. Input/output or analog input or V REF Input/output or analog input or V ...
Page 130
... PIC18F6585/8585/6680/8680 10.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 131
... To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2<7>). 3: For PIC18FXX85 parts, the CCP2 input/output is multiplexed with RB3 if the CCP2MX bit is enabled (= 0) in the Configuration register and the device is operating in Microprocessor, Microprocessor with Boot Block or Extended Microcontroller mode. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 V DD Weak P ...
Page 132
... PIC18F6585/8585/6680/8680 TABLE 10-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT0 bit 0 TTL/ST RB1/INT1 bit 1 TTL/ST RB2/INT2 bit 2 TTL/ST (3) RB3/INT3/CCP2 bit 3 TTL/ST RB4/KBI0 bit 4 TTL RB5/KBI1/PGM bit 5 TTL/ST RB6/KBI2/PGC bit 6 TTL/ST RB7/KBI3/PGD bit 7 TTL/ST Legend: TTL = TTL input Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. ...
Page 133
... Note 1: I/O pins have diode protection Peripheral output enable is only active if peripheral select is active. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 The pin override value is not loaded into the TRIS reg- ister. This allows read-modify-write of the TRIS register without concern due to peripheral overrides. ...
Page 134
... PIC18F6585/8585/6680/8680 TABLE 10-5: PORTC FUNCTIONS Name Bit# Buffer Type RC0/T1OSO/T13CKI bit 0 ST (1) RC1/T1OSI/CCP2 bit 1 ST RC2/CCP1/P1A bit 2 ST RC3/SCK/SCL bit 3 ST RC4/SDI/SDA bit 4 ST RC5/SDO bit 5 ST RC6/TX/CK bit 6 ST RC7/RX/DT bit 7 ST Legend Schmitt Trigger input Note 1: RB3 is the alternate assignment for CCP2 when CCP2MX is set. ...
Page 135
... Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISD ; Set RD<3:0> as inputs ; RD<5:4> as outputs ; RD<7:6> as inputs 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 FIGURE 10-9: RD LATD Data Bus D WR LATD or PORTD CK Data Latch D WR TRISD CK TRIS Latch ...
Page 136
... PIC18F6585/8585/6680/8680 FIGURE 10-10: PORTD BLOCK DIAGRAM IN SYSTEM BUS MODE (PIC18F8X8X ONLY) RD PORTD RD LATD Data Bus WR LATD or PORTD WR TRISD RD TRISD Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V DS30491C-page 134 ...
Page 137
... EBDIS — WAIT1 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function (1) Input/output port pin, Parallel Slave Port bit 0 or address/data bus bit 0. (1) Input/output port pin, Parallel Slave Port bit 1 or address/data bus bit 1. ...
Page 138
... PIC18F6585/8585/6680/8680 10.5 PORTE, TRISE and LATE Registers PORTE is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i ...
Page 139
... RD LATE Data Bus WR LATE or PORTE WR TRISE RD TRISE Bus Enable System Bus Data/TRIS Out Control Drive Bus Instruction Register Instruction Read Note 1: I/O pins have protection diodes to V 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 I/O pin TRIS Pin Override RE0 RE1 RE2 ...
Page 140
... PIC18F6585/8585/6680/8680 TABLE 10-9: PORTE FUNCTIONS Name Bit# Buffer Type (2) RE0/RD/AD8 bit 0 ST/TTL (2) RE1/WR/AD9 bit 1 ST/TTL (2) RE2/CS/AD10 bit 2 ST/TTL (2) RE3/AD11 bit 3 ST/TTL (2) RE4/AD12 bit 4 ST/TTL (2) (3) RE5/AD13/ P1C bit 5 ST/TTL (2) (3) RE6/AD14/ P1B bit 6 ST/TTL (2) RE7/CCP2/AD15 bit 7 ST/TTL Legend Schmitt Trigger input, TTL = TTL input ...
Page 141
... WR PORTF CK Q Data Latch TRISF Q CK TRIS Latch RD TRISF RD PORTF To A/D Converter Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 EXAMPLE 10-6: CLRF PORTF CLRF LATF MOVLW 07h MOVWF CMCON MOVLW 0Fh MOVWF ADCON1 MOVLW 0CFh ...
Page 142
... PIC18F6585/8585/6680/8680 FIGURE 10-14: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM RD LATF Data Bus LATF or WR PORTF CK Q Data Latch TRISF CK Q Analog Input TRIS Latch Mode RD TRISF PORTF To A/D Converter or Comparator Input Note 1: I/O pins have diode protection to V DS30491C-page 140 FIGURE 10-15: ...
Page 143
... CVRCON CVREN CVROE CVRR CVRSS CVR3 Legend unknown unchanged. Shaded cells are not used by PORTF. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function Input/output port pin or analog input. Input/output port pin, analog input or comparator 2 output. Input/output port pin, analog input or comparator 1 output. ...
Page 144
... PIC18F6585/8585/6680/8680 10.7 PORTG, TRISG and LATG Registers PORTG is a 6-bit wide port with 5 bidirectional pins and 1 unidirectional pin. The corresponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 145
... WR PORTG Data Latch D Q Schmitt Trigger WR TRISG CK Input Buffer TRIS Latch RD TRISG PORTG CANRX Note: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 TX1SRC OPMODE2:OPMODE0 = 000 and FIGURE 10-19: Data Bus I/O pin WR LATG or WR PORTG ...
Page 146
... PIC18F6585/8585/6680/8680 FIGURE 10-20: RG4/P1D PIN BLOCK DIAGRAM CCP1 P1D Enable RD LATG Data Bus D WR LATG PORTG Data Latch D WR TRISG CK TRIS Latch RD PORTG Note: I/O pins have diode protection to V FIGURE 10-21: RG5/MCLR/V MCLRE Data Bus RD TRISA RD LATA RD PORTA High-Voltage Detect ...
Page 147
... Legend unknown unchanged Note 1: RG5 is available as an input only when MCLR is disabled. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function Input/output port pin or CAN bus transmit output. Input/output port pin, CAN bus complimentary transmit output or CAN bus bit time clock. Input/output port pin or CAN bus receive. ...
Page 148
... PIC18F6585/8585/6680/8680 10.8 PORTH, LATH and TRISH Registers Note: PORTH is available only on PIC18F8X8X devices. PORTH is an 8-bit wide, bidirectional I/O port. The cor- responding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 149
... RD PORTH RD LATD Data Bus WR LATH or PORTH WR TRISH RD TRISH External Enable System Bus Address Out Control Drive System To Instruction Register Instruction Read Note 1: I/O pins have diode protection to V 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Port Data 1 CK Data Latch TRIS Latch and V ...
Page 150
... PIC18F6585/8585/6680/8680 TABLE 10-15: PORTH FUNCTIONS Name Bit# Buffer Type RH0/A16 bit 0 ST/TTL RH1/A17 bit 1 ST/TTL RH2/A18 bit 2 ST/TTL RH3/A19 bit 3 ST/TTL RH4/AN12 bit 4 ST RH5/AN13 bit 5 ST (2) RH6/AN14/P1C bit 6 ST (2) RH7/AN15/P1B bit 7 ST Legend Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in System Bus or Parallel Slave Port mode ...
Page 151
... Alternate method ; to clear output ; data latches MOVLW 0CFh ; Value used to ; initialize data ; direction MOVWF TRISJ ; Set RJ3:RJ0 as inputs ; RJ5:RJ4 as output ; RJ7:RJ6 as inputs 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 FIGURE 10-25: RD LATJ Data Bus D WR LATJ CK or PORTJ Data Latch D WR TRISJ CK ...
Page 152
... PIC18F6585/8585/6680/8680 FIGURE 10-26: RJ5:RJ0 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE RD PORTJ RD LATJ Data Bus WR LATJ or PORTJ WR TRISJ RD TRISJ Control Out System Bus External Enable Control Drive System Note 1: I/O pins have diode protection to V FIGURE 10-27: RJ7:RJ6 PINS BLOCK DIAGRAM IN SYSTEM BUS MODE ...
Page 153
... LATJ Data Output Register TRISJ Data Direction Control Register for PORTJ Legend unknown unchanged 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Function Input/output port pin or address latch enable control for external memory interface. Input/output port pin or output enable control for external memory interface ...
Page 154
... PIC18F6585/8585/6680/8680 10.10 Parallel Slave Port (PSP) PORTD also operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set asynchronously readable and writable by the external world through RD control input pin, RE0/RD/AD8 and WR control input pin, RE1/WR/AD9. Note: ...
Page 155
... Value at POR FIGURE 10-29: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Q3 ...
Page 156
... PIC18F6585/8585/6680/8680 FIGURE 10-30: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 10-19: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 PORTD Port Data Latch when Written; Port pins when Read LATD LATD Data Output bits TRISD PORTD Data Direction bits ...
Page 157
... Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Figure 11-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register (Register 11- readable and writable register that controls all the aspects of Timer0, including the prescale selection ...
Page 158
... PIC18F6585/8585/6680/8680 FIGURE 11-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE OSC 1 RA4/T0CKI pin T0SE T0CS Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 11-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE OSC 1 Programmable T0CKI pin Prescaler T0SE T0PS2, T0PS1, T0PS0 ...
Page 159
... PORTA Data Direction Register Legend unknown unchanged, – = unimplemented locations, read as ‘0’. Shaded cells are not used by Timer0. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 11.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution) ...
Page 160
... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 158 2004 Microchip Technology Inc. ...
Page 161
... Stops Timer1 Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Figure 12 simplified block diagram of the Timer1 module. Register 12-1 details the Timer1 Control register. This register controls the operating mode of the Timer1 module and contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON< ...
Page 162
... PIC18F6585/8585/6680/8680 12.1 Timer1 Operation Timer1 can operate in one of these modes: • timer • synchronous counter • asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). FIGURE 12-1: TIMER1 BLOCK DIAGRAM TMR1IF Overflow Interrupt Flag Bit TMR1H T1OSC T13CKI/T1OSO T1OSI Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off ...
Page 163
... T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 12.4 Resetting Timer1 Using a CCP Trigger Output If the CCP module is configured in Compare mode ...
Page 164
... PIC18F6585/8585/6680/8680 13.0 TIMER2 MODULE The Timer2 module timer has the following features: • 8-bit timer (TMR2 register) • 8-bit period register (PR2) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4, 1:16) • Software programmable postscaler (1:1 to 1:16) • ...
Page 165
... Timer2 Period Register Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 13.3 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the synchronous serial port module which optionally uses it to generate the shift clock ...
Page 166
... PIC18F6585/8585/6680/8680 14.0 TIMER3 MODULE The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers; TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt on overflow from FFFFh to 0000h • Reset from CCP module trigger ...
Page 167
... T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 When TMR3CS = 0, Timer3 increments every instruc- tion cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator if enabled ...
Page 168
... PIC18F6585/8585/6680/8680 14.2 Timer1 Oscillator The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a low- power oscillator rated up to 200 kHz. See Section 12.0 “Timer1 Module” for further details. ...
Page 169
... PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 Additionally, the CCP2 special event trigger may be used to start an A/D conversion if the A/D module is enabled. To avoid duplicate information, this section describes basic CCP module operation that applies to both CCP1 and CCP2 ...
Page 170
... PIC18F6585/8585/6680/8680 REGISTER 15-2: CCP2CON REGISTER U-0 — bit 7 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DC2B1:DC2B0: PWM Duty Cycle bit 1 and bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in CCPR2L ...
Page 171
... None. PWM Compare None. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 An event is selected by control bits CCPxM3:CCPxM0 (CCPxCON<3:0>). When a capture is made, the inter- rupt request flag bit, CCPxIF (PIR registers), is set. It must be cleared in software. If another capture occurs before the value in register CCPRx is read, the old captured value will be lost ...
Page 172
... PIC18F6585/8585/6680/8680 15.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCPxIE (PIE registers) clear to avoid false interrupts and should clear the flag bit, CCPxIF, following any such change in operating mode. 15.2.4 CCP PRESCALER There are four prescaler settings specified by bits CCPxM3:CCPxM0 ...
Page 173
... RC1/CCP2 pin R TRISC<1> Output Enable CCP2CON<3:0> 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 15.3.2 TIMER1/TIMER3 MODE SELECTION The timer used with each CCP module is selected in the T3CCP2:T3CCP1 bits of the T3CON register. Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature ...
Page 174
... PIC18F6585/8585/6680/8680 TABLE 15-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Name Bit 7 Bit 6 Bit 5 INTCON GIE/ PEIE/ TMR0IE GIEH GIEL PIR1 PSPIF ADIF RCIF PIE1 PSPIE ADIE RCIE IPR1 PSPIP ADIP RCIP TRISD PORTD Data Direction Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register ...
Page 175
... PWM OUTPUT Period Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 15.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula. EQUATION 15-1: PWM Period = [(PR2 • 4 • T PWM frequency is defined as 1/[PWM period] ...
Page 176
... PIC18F6585/8585/6680/8680 The maximum PWM resolution (bits) for a given PWM frequency is given by the following equation. EQUATION 15-3: F OSC --------------- log F PWM PWM Resolution (max) = -----------------------------bits log 2 Note: If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared ...
Page 177
... PWM mode; P1A, P1C active-low; P1B, P1D active-low Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 The control register for CCP1 is shown in Register 16-1. In addition to the expanded functions of the CCP1CON register, the CCP1 module has two additional registers associated with enhanced PWM operation and auto-shutdown features: • ...
Page 178
... PIC18F6585/8585/6680/8680 16.1 ECCP Outputs The enhanced CCP module may have up to four outputs depending on the selected operating mode. These outputs, designated P1A through P1D, are multiplexed with I/O pins RC2, RE6, RE5 and RG4. The pin assignments are summarized in Table 16-1. ...
Page 179
... PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 16.2.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON< ...
Page 180
... PIC18F6585/8585/6680/8680 TABLE 16-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency 2.44 kHz Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) FIGURE 16-2: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODULE CCP1CON<5:4> Duty Cycle Registers CCPR1L CCPR1H (Slave) Comparator (Note 1) ...
Page 181
... Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 16.2.6 “Programmable Dead-Band Delay”). Relationships: • Period = (PR2 + 1) * (TMR2 prescale value) OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 prescale value) OSC • Delay = (PWM1CON<6:0>) OSC 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 0 Duty Cycle Period (1) Delay Delay PR2 + 1 (1) DS30491C-page 179 ...
Page 182
... PIC18F6585/8585/6680/8680 16.2.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin while the complementary PWM output signal is output on the P1B pin (Figure 16-5). This mode can be used for half-bridge applications, as ...
Page 183
... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: Output signal is shown as active-high. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 P1A, P1B, P1C and P1D outputs are multiplexed with the PORTC<2>, PORTE<6:5> and PORTG<4> data latches. The TRISC<2>, TRISC<6:5> and TRISG<4> ...
Page 184
... PIC18F6585/8585/6680/8680 FIGURE 16-8: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18FXX80/XX85 P1A P1B P1C P1D 16.2.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows the user to control the forward/reverse direction. When the firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
Page 185
... Note 1: All signals are shown as active-high the turn on delay of power switch QC and its driver the turn off delay of power switch QD and its driver. OFF 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 (1) Period DC (Note 2) , depending on the Timer2 prescaler value. The modulated P1B and P1D OSC Forward Period ...
Page 186
... PIC18F6585/8585/6680/8680 16.2.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on ...
Page 187
... Drive pins B and D to ‘0’ Drive pins B and D to ‘1’ Pins B and D tri-state Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared ...
Page 188
... PIC18F6585/8585/6680/8680 16.2.7.1 Auto-Shutdown and Automatic Restart The auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. This is enabled by setting the PRSEN bit of the ECCP1DEL register (ECCP1DEL<7>). In Shutdown mode with PRSEN = 1 (Figure 16-11), the ECCPASE bit will remain set for as long as the cause of the shutdown continues ...
Page 189
... PRSEN PDC6 PDC5 Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 7. If auto-restart operation is required, set the PRSEN bit (ECCP1DEL<7>). 8. Configure and start TMR2: • Clear the TMR2 interrupt flag bit by clearing the TMR2IF bit (PIR1< ...
Page 190
... PIC18F6585/8585/6680/8680 NOTES: DS30491C-page 188 2004 Microchip Technology Inc. ...
Page 191
... MSSP 2 module is operated in SPI mode. Additional details are provided under the individual sections. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 17.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of ...
Page 192
... PIC18F6585/8585/6680/8680 17.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPCON1) • MSSP Status Register (SSPSTAT) • Serial Receive/Transmit Buffer Register (SSPBUF) • MSSP Shift Register (SSPSR) – Not directly accessible SSPCON1 and SSPSTAT are the control and status registers in SPI mode operation ...
Page 193
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit - n = Value at POR 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 /64 OSC /16 OSC ...
Page 194
... PIC18F6585/8585/6680/8680 17.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCK is the clock output) • Slave mode (SCK is the clock input) • ...
Page 195
... Shift Register (SSPSR) MSb LSb PROCESSOR 1 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 17.3.4 TYPICAL CONNECTION Figure 17-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their pro- grammed clock edge and latched on the opposite edge of the clock ...
Page 196
... PIC18F6585/8585/6680/8680 17.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 17- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be dis- abled (programmed as an input) ...
Page 197
... Interrupt Flag SSPSR to SSPBUF 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled (SSPCON< ...
Page 198
... PIC18F6585/8585/6680/8680 FIGURE 17-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 17-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
Page 199
... D/A Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode. 2004 Microchip Technology Inc. PIC18F6585/8585/6680/8680 17.3.10 BUS MODE COMPATIBILITY Table 17-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits ...
Page 200
... PIC18F6585/8585/6680/8680 2 17 Mode 2 The MSSP module mode fully implements all master and slave functions (including general call sup- port) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master func- tion). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing ...