PIC18F6585-I/L Microchip Technology, PIC18F6585-I/L Datasheet - Page 172

• Manufacturer Part Number: PIC18F6585-I/L
• Description: Microcontrollers (MCU) 48KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6585-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 48 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F6585/8585/6680/8680
15.2.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCPxIE (PIE registers) clear to avoid false interrupts
and should clear the flag bit, CCPxIF, following any
such change in operating mode.
15.2.4
There are four prescaler settings specified by bits
CCPxM3:CCPxM0. Whenever the CCPx module is
turned off, or the CCPx module is not in Capture mode,
the prescaler counter is cleared. This means that any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. The prescaler counter will not be
cleared; therefore, the first capture may be from a
non-zero
recommended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
FIGURE 15-1:
DS30491C-page 170
CCP1 pin
CCP2 pin
SOFTWARE INTERRUPT
CCP PRESCALER
prescaler.
CAPTURE MODE OPERATION BLOCK DIAGRAM
Q’s
Edge Detect
Edge Detect
Q’s
Prescaler
Prescaler
Example 15-1
1, 4, 16
1, 4, 16
and
and
CCP1CON<3:0>
CCP2CON<3:0>
Set Flag bit CCP2IF
Set Flag bit CCP1IF
shows
T3CCP1
T3CCP2
T3CCP2
T3CCP1
the
T3CCP2
T3CCP2
15.2.5
The CAN capture event occurs when a message is
received in any of the receive buffers. When config-
ured, the CAN module provides the trigger to the CCP1
module to cause a capture event. This feature is
provided to time-stamp the received CAN messages.
This feature is enabled by setting the CANCAP bit of
the CAN I/O Control register (CIOCON<4>). The
message receive signal from the CAN module then
takes the place of the events on RC2/CCP1.
EXAMPLE 15-1:
CLRF
MOVLW
MOVWF
CCP1CON
NEW_CAPT_PS
CCP1CON
CAN MESSAGE TIME-STAMP
TMR1
Enable
TMR1
Enable
TMR3
Enable
TMR3
Enable
CCPR1H
CCPR2H
TMR1H
TMR1H
TMR3H
TMR3H
CHANGING BETWEEN
CAPTURE PRESCALERS
 2004 Microchip Technology Inc.
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
CCPR1L
CCPR2L
TMR3L
TMR1L
TMR3L
TMR1L