PIC18F6585-I/L Microchip Technology, PIC18F6585-I/L Datasheet - Page 199

• Manufacturer Part Number: PIC18F6585-I/L
• Description: Microcontrollers (MCU) 48KB 3328 RAM 52 I/O
• Manufacturer: Microchip Technology

Specifications of PIC18F6585-I/L

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3.25 KB
• Interface Type: I2C/SPI/AUSART/CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12-ch x 10-bit
• Program Memory Type: Flash
• Program Memory Size: 48 KB
• Package / Case: PLCC-68
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.3.8
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal
transmit/receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the MSSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
17.3.9
A Reset disables the MSSP module and terminates the
current transfer.
TABLE 17-2:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISC
TRISF
SSPBUF
SSPCON
SSPSTAT
Legend:
Name
mode,
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
SLEEP OPERATION
EFFECTS OF A RESET
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
TRISF7
PSPIE
PSPIP
WCOL
PSPIF
Bit 7
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
the
module
TRISF6
SSPOV
ADIE
ADIP
Bit 6
ADIF
CKE
will
TRISF5
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
continue
PIC18F6585/8585/6680/8680
TRISF4
INT0IE
Bit 4
TXIF
TXIE
TXIP
CKP
P
to
TRISF3
SSPM3
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
S
17.3.10
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also a SMP bit which controls when the data is
sampled.
Standard SPI Mode
TMR0IF
CCP1IE
CCP1IP
CCP1IF
TRISF2
SSPM2
Bit 2
R/W
Terminology
0, 0
0, 1
1, 0
1, 1
BUS MODE COMPATIBILITY
TMR2IE
TMR2IP
TMR2IF
TRISF1
SSPM1
INT0IF
Bit 1
UA
SPI BUS MODES
TMR1IE 0000 0000 0000 0000
TMR1IP 1111 1111 1111 1111
TMR1IF 0000 0000 0000 0000
TRISF0 1111 1111 uuuu uuuu
SSPM0 0000 0000 0000 0000
RBIF
Bit 0
BF
CKP
Control Bits State
0000 0000 0000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0
0
1
1
POR, BOR
Value on
DS30491C-page 197
CKE
Value on
all other
Resets
1
0
1
0