PIC24F08KA101-I/SO Microchip Technology, PIC24F08KA101-I/SO Datasheet - Page 56

• Manufacturer Part Number: PIC24F08KA101-I/SO
• Description: IC PIC MCU FLASH 8K 20-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F08KA101-I/SO

• Core Size: 16-Bit
• Program Memory Size: 8KB (2.75K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Controller Family/series: PIC24
• No. Of I/o's: 18
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1.5KB
• Cpu Speed: 32MHz
• No. Of Timers: 3
• Core: PIC
• Processor Series: PIC24F
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 32 KHz
• Data Ram Size: 1.5 KB
• On-chip Adc: 10 bit, 9 Channel
• Number Of Programmable I/os: 18
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 2.05 mm
• Interface Type: I2C, IrDA, SPI, UART
• Length: 12.8 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.8 V
• Width: 7.5 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / Rohs Status: Details

PIC24F16KA102 FAMILY
6.4.1
The data EEPROM can be fully erased, or can be
partially erased, at three different sizes: one word, four
words or eight words. The bits, NVMOP<1:0>
(NVMCON<1:0>), decide the number of words to be
erased. To erase partially from the data EEPROM, the
following sequence must be followed:
1.
2.
3.
4.
5.
6.
EXAMPLE 6-2:
DS39927B-page 54
int __attribute__ ((space(eedata))) eeData = 0x1234; // Variable located in EEPROM
Configure NVMCON to erase the required
number of words: one, four or eight.
Load TBLPAG and WREG with the EEPROM
address to be erased.
Clear NVMIF status bit and enable NVM
interrupt (optional).
Write the key sequence to NVMKEY.
Set the WR bit to begin erase cycle.
Either poll the WR bit or wait for the NVM
interrupt (NVMIF set).
unsigned int offset;
// Set up NVMCON to erase one word of data EEPROM
NVMCON = 0x4058;
// Set up a pointer to the EEPROM location to be erased
TBLPAG = __builtin_tblpage(&eeData);
offset = __builtin_tbloffset(&eeData);
__builtin_tblwtl(offset, 0);
asm volatile ("disi #5");
__builtin_write_NVM();
ERASE DATA EEPROM
SINGLE-WORD ERASE
Preliminary
// Initialize EE Data page pointer
// Initizlize lower word of address
// Write EEPROM data to write latch
// Disable Interrupts For 5 Instructions
// Issue Unlock Sequence & Start Write Cycle
A typical erase sequence is provided in Example 6-2.
This example shows how to do a one-word erase. Sim-
ilarly, a four-word erase and an eight-word erase can
be done. This example uses C library procedures to
manage the Table Pointer (builtin_tblpage and
builtin_tbloffset) and the Erase Page Pointer
(builtin_tblwtl). The memory unlock sequence
(builtin_write_NVM) also sets the WR bit to initiate
the operation and returns control when complete.
© 2009 Microchip Technology Inc.