PIC12C672-10/SM Microchip Technology, PIC12C672-10/SM Datasheet - Page 127
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PIC12C672-10/SM
Manufacturer Part Number
PIC12C672-10/SM
Description
IC MCU OTP 2KX14 A/D 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12CE673-10P.pdf
(129 pages)
3.PIC12CE673-10P.pdf
(14 pages)
Specifications of PIC12C672-10/SM
Core Processor
PIC
Core Size
8-Bit
Speed
10MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Other names
PIC12C672-10/SMR
PIC12C672-10/SMR
PIC12C672-10/SMR
- Current page: 127 of 688
- Download datasheet (3Mb)
8.2
8.2.1
1997 Microchip Technology Inc.
INTCON Register
Control Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Generally devices have a minimum of three registers associated with interrupts. The INTCON
register which contains Global Interrupt Enable bit, GIE, as well as the Peripheral Interrupt
Enable bit, PEIE, and the PIE / PIR register pair which enable the peripheral interrupts and dis-
play the interrupt flag status.
The INTCON Register is a readable and writable register which contains various enable and flag
bits.
Register 8-1: INTCON Register
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt
0 = Disables the INT external interrupt
RBIE
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
RBIF
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend
R = Readable bit
U = Unimplemented bit, read as ‘0’
R/W-0
Note 1: In some devices, the RBIE bit may also be known as GPIE and the RBIF bit may be
Note 2: Some devices may not have this feature. For those devices this bit is reserved.
Note 3: In devices with only one peripheral interrupt, this bit may be EEIE or ADIE.
Note:
GIE
(1)
(1)
: RB Port Change Interrupt Flag bit
: RB Port Change Interrupt Enable bit
know as GPIF.
Interrupt flag bits get set when an interrupt condition occurs regardless of the state
of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).This
feature allows for software polling.
PEIE
R/W-0
(3)
W = Writable bit
R/W-0
T0IE
INTE
R/W-0
Section 8. Interrupts
(2)
- n = Value at POR reset
RBIE
R/W-0
2)
(1,
R/W-0
T0IF
INTF
R/W-0
DS31008A-page 8-5
(2)
bit 0
RBIF
R/W-0
(1, 2)
8
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