PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 12
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PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC18F1XK50/PIC18LF1XK50
4.0
Programming includes the ability to erase or write the
various memory regions within the device.
In all cases, except high-voltage ICSP Bulk Erase, the
EECON1 register must be configured in order to
operate on a particular memory region.
When using the EECON1 register to act on program
Flash, the EEPGD bit must be set (EECON1<7> = 1)
and the CFGS bit must be cleared (EECON1<6> = 0).
The WREN bit must be set (EECON1<2> = 1) to
enable writes of any sort (e.g., erases) and this must be
done prior to initiating a write sequence. The FREE bit
must be set (EECON1<4> = 1) in order to erase the
program space being pointed to by the Table Pointer.
The erase or write sequence is initiated by setting the
WR bit (EECON1<1> = 1). It is strongly recommended
that the WREN bit only be set immediately, prior to a
program or erase.
4.1
4.1.1
Erasing program Flash or data EEPROM is accom-
plished by configuring two Bulk Erase Control registers,
located at 3C0004h and 3C0005h. Program Flash may
be erased portions at a time, or the user may erase the
entire device in one action. Bulk Erase operations will
also clear any code-protect settings associated with the
memory block erased. Erase options are detailed in
Table 4-1.
(CPD = 0), the user must request an erase of data
EEPROM (e.g., 0084h as shown in Table 4-1).
TABLE 4-1:
The actual Bulk Erase function is a self-timed
operation. Once the erase has started (falling edge of
the 4th PGC after the NOP command), serial execution
will cease until the erase completes (parameter P11).
During this time, PGC may continue to toggle but PGD
must be held low.
DS41342E-page 12
Chip Erase
Erase User IDs
Erase Data EEPROM
Erase Boot Block
Erase Config Bits
Erase Program Flash Block 0
Erase Program Flash Block 1
Erase Program Flash Block 2
Erase Program Flash Block 3
DEVICE PROGRAMMING
ICSP Erase
Description
HIGH-VOLTAGE ICSP BULK ERASE
If
data
BULK ERASE OPTIONS
EEPROM
(3C0005h:3C0004h)
is
code-protected
0F8Fh
0088h
0081h
0180h
0280h
0480h
0880h
0084h
0082h
Data
Advance Information
The code sequence to erase the entire device is shown
in Table 4-2 and the flowchart is shown in Figure 4-1.
TABLE 4-2:
FIGURE 4-1:
Command
Note:
0000
0000
0000
0000
0000
0000
1100
0000
0000
0000
0000
0000
0000
1100
0000
0000
4-Bit
A Bulk Erase is the only way to reprogram
code-protect bits from an “on” state to an
“off” state.
Payload
0E 3C
0E 3C
6E F8
0E 00
6E F7
0E 05
6E F6
0F 0F
6E F8
0E 00
6E F7
0E 04
6E F6
8F 8F
00 00
00 00
Data
3C0004h to Erase
Delay P11 + P10
BULK ERASE COMMAND
SEQUENCE
Write 8F8Fh to
Entire Device
Write 0F0Fh
to 3C0005h
BULK ERASE FLOW
Done
Time
Start
2010 Microchip Technology Inc.
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 05h
MOVWF TBLPTRL
Write 0Fh to 3C0005h
MOVLW 3Ch
MOVWF TBLPTRU
MOVLW 00h
MOVWF TBLPTRH
MOVLW 04h
MOVWF TBLPTRL
Write 8F8Fh TO 3C0004h
to erase entire device.
NOP
Hold PGD low until erase
completes.
Core Instruction