PIC18LF13K50-I/P Microchip Technology, PIC18LF13K50-I/P Datasheet - Page 259
![IC PIC MCU FLASH 4KX16 20-PDIP](/photos/12/13/121303/150-20-dip_sml.jpg)
PIC18LF13K50-I/P
Manufacturer Part Number
PIC18LF13K50-I/P
Description
IC PIC MCU FLASH 4KX16 20-PDIP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F13K50-ISS.pdf
(420 pages)
2.PIC18F13K50-ISS.pdf
(40 pages)
3.PIC18F13K50-ISS.pdf
(10 pages)
4.PIC18F13K50-ISS.pdf
(2 pages)
5.PIC18F13K50-ISO.pdf
(414 pages)
Specifications of PIC18LF13K50-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
14
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Controller Family/series
PIC18
No. Of I/o's
15
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
48MHz
No. Of Timers
4
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART, I2C, MSSP, SPI, USB
Maximum Clock Frequency
32 KHz
Number Of Programmable I/os
18
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
- PIC18F13K50-ISS PDF datasheet
- PIC18F13K50-ISS PDF datasheet #2
- PIC18F13K50-ISS PDF datasheet #3
- PIC18F13K50-ISS PDF datasheet #4
- PIC18F13K50-ISO PDF datasheet #5
- Current page: 259 of 414
- Download datasheet (4Mb)
22.4.4
An endpoint is defined to have a ping-pong buffer when
it has two sets of BD entries: one set for an Even
transfer and one set for an Odd transfer. This allows the
CPU to process one BD while the SIE is processing the
other BD. Double-buffering BDs in this way allows for
maximum throughput to/from the USB.
The USB module supports four modes of operation:
• No ping-pong support
• Ping-pong buffer support for OUT Endpoint 0 only
• Ping-pong buffer support for all endpoints
• Ping-pong buffer support for all other Endpoints
The ping-pong buffer settings are configured using the
PPB<1:0> bits in the UCFG register.
The USB module keeps track of the Ping-Pong Pointer
individually for each endpoint. All pointers are initially
reset to the Even BD when the module is enabled. After
FIGURE 22-6:
© 200C Microchip Technology Inc.
2FFh
200h
23Fh
except Endpoint 0
Note:
Maximum Memory
Used: 64 bytes
Maximum BDs:
16 (BD0 to BD15)
PPB<1:0> = 00
No Ping-Pong
Data RAM
Available
Buffers
as
PING-PONG BUFFERING
Memory area not shown to scale.
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP7 IN
Descriptor
BUFFER DESCRIPTOR TABLE MAPPING FOR BUFFERING MODES
2FFh
200h
243h
Ping-Pong Buffer
Maximum Memory
Used: 68 bytes
Maximum BDs:
17 (BD0 to BD16)
PPB<1:0> = 01
on EP0 OUT
Data RAM
Available
as
PIC18F1XK50/PIC18LF1XK50
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN
Descriptor
EP1 OUT
Descriptor
EP1 IN
Descriptor
EP7 IN
Descriptor
Preliminary
2FFh
27Fh
200h
Ping-Pong Buffers
Maximum Memory
Used: 128 bytes
Maximum BDs:
32 (BD0 to BD31)
PPB<1:0> = 10
on all EPs
the completion of a transaction (UOWN cleared by the
SIE), the pointer is toggled to the Odd BD. After the
completion of the next transaction, the pointer is
toggled back to the Even BD and so on.
The Even/Odd status of the last transaction is stored in
the PPBI bit of the USTAT register. The user can reset
all Ping-Pong Pointers to Even using the PPBRST bit.
Figure 22-6 shows the four different modes of
operation and how USB RAM is filled with the BDs.
BDs have a fixed relationship to a particular endpoint,
depending on the buffering configuration. The mapping
of BDs to endpoints is detailed in Table 22-2. This
relationship also means that gaps may occur in the
BDT if endpoints are not enabled contiguously. This
theoretically means that the BDs for disabled endpoints
could be used as buffer space. In practice, users
should avoid using such spaces in the BDT unless a
method of validating BD addresses is implemented.
EP0 OUT Even
Descriptor
EP0 OUT Odd
Descriptor
EP0 IN Even
Descriptor
EP0 IN Odd
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Even
Descriptor
EP1 IN Odd
Descriptor
EP7 IN Odd
Descriptor
277h
2FFh
200h
Ping-Pong Buffers
Maximum Memory
Used: 120 bytes
Maximum BDs:
30 (BD0 to BD29)
on all other EPs
PPB<1:0> = 11
Data RAM
Available
except EP0
as
DS41350C-page 257
EP0 OUT
Descriptor
EP0 IN
Descriptor
EP1 OUT Even
Descriptor
EP1 OUT Odd
Descriptor
EP1 IN Odd
Descriptor
EP7 IN Odd
Descriptor
EP1 IN Even
Descriptor
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