PIC16F627-04I/P Microchip Technology, PIC16F627-04I/P Datasheet - Page 17
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PIC16F627-04I/P
Manufacturer Part Number
PIC16F627-04I/P
Description
IC MCU FLASH 1KX14 COMP 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheet
1.PIC16F627-04P.pdf
(170 pages)
Specifications of PIC16F627-04I/P
Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
4MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
224 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
128Byte
Ram Memory Size
224Byte
Cpu Speed
4MHz
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
224 B
Interface Type
SCI, USART
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
16
Number Of Timers
8
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DVA16XP183 - ADAPTER ICE 18DIP/SOIC/SSOPAC164010 - MODULE SKT PROMATEII DIP/SOIC
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F627-04I/P
Manufacturer:
MICR
Quantity:
20 000
3.2.2
The SFRs are registers used by the CPU and Periph-
eral functions for controlling the desired operation of
the device (Table 3-1). These registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The SFRs associated with the
“core” functions are described in this section. Those
related to the operation of the peripheral features are
described in the section of that peripheral feature.
TABLE 3-1:
2003 Microchip Technology Inc.
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note 1: For the Initialization Condition for Registers Tables, refer to Table 14-7 and Table 14-8 on page 98.
Address
shaded = unimplemented
— = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CMCON
SPECIAL FUNCTION REGISTERS
Name
—
—
—
—
—
—
—
—
—
—
SPECIAL REGISTERS SUMMARY BANK 0
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 Module’s Register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Holding register for the Least Significant Byte of the 16-bit TMR1
Holding register for the Most Significant Byte of the 16-bit TMR1
TMR2 module’s register
Unimplemented
Unimplemented
Capture/Compare/PWM register (LSB)
Capture/Compare/PWM register (MSB)
USART Transmit data register
USART Receive data register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
C2OUT
Bit 7
SPEN
EEIF
RA7
RB7
IRP
GIE
—
—
—
—
TOUTPS3
C1OUT
Bit 6
CMIF
PEIE
RP1
RA6
RB6
RX9
—
—
—
T1CKPS1
TOUTPS2
CCP1X
C2INV
Bit 5
SREN
RCIF
T0IE
RP0
RA5
RB5
—
Write buffer for upper 5 bits of program counter
Preliminary
TOUTPS1
T1CKPS0
CCP1Y
C1INV
Bit 4
CREN
INTE
TXIF
RA4
RB4
TO
T1OSCEN
TOUTPS0
CCP1M3
Bit 3
ADEN
RBIE
RA3
RB3
CIS
PD
—
TMR2ON
CCP1M2
T1SYNC
CCP1IF
Bit 2
FERR
RB2
T0IF
CM2
RA2
Z
T2CKPS1 T2CKPS0
TMR1CS
CCP1M1
TMR2IF
OERR
Bit 1
INTF
CM1
RA1
RB1
DC
PIC16F62X
TMR1ON
CCP1M0
TMR1IF
Bit 0
RX9D
RBIF
CM0
RA0
RB0
C
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
xxxx 0000
xxxx xxxx
---0 0000
0000 000x
0000 -000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 -00x
0000 0000
0000 0000
0000 0000
Value on
DS40300C-page 15
Reset
POR
—
—
—
—
—
—
—
—
—
—
(1)
on Page
Details
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