PIC18F26K20-E/SS Microchip Technology, PIC18F26K20-E/SS Datasheet - Page 4
![IC PIC MCU FLASH 32KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18F26K20-E/SS
Manufacturer Part Number
PIC18F26K20-E/SS
Description
IC PIC MCU FLASH 32KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheets
1.PIC18F25K20T-ISS.pdf
(42 pages)
2.PIC18F25K20T-ISS.pdf
(456 pages)
3.PIC18F26K20-ISS.pdf
(6 pages)
4.PIC18F26K20-ISS.pdf
(10 pages)
5.PIC18F26K20-EML.pdf
(430 pages)
Specifications of PIC18F26K20-E/SS
Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1024Byte
Ram Memory Size
3.84375KB
Cpu Speed
64MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28SSOP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164307 - MODULE SKT FOR PM3 28SSOP
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18F26K20-E/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC18F26K20/46K20
6. Module: EUSART
7. Module: EUSART
8. Module: System Clocks
DS80404E-page 4
The OERR flag of the RCSTA register is reset only
by clearing the CREN bit of the RCSTA register or
by a device Reset. Clearing the SPEN bit of the
RCSTA register does not clear the OERR flag.
Work around
Clear the OERR flag by clearing the CREN bit
instead of clearing the SPEN bit.
Affected Silicon Revisions
In Asynchronous Receive mode when the RX
input goes low after an Idle period and stays low
for less than 1/16th bit period then that event will
be correctly detected as an invalid Start bit. If the
RX input goes low a second time less than one full
bit time after the leading edge of the first invalid
Start time then the low transition of the RCIDL
Status bit will be improperly delayed by one full bit
time following that second edge. If the second
pulse is also an invalid Start bit then the RCIDL will
remain low indefinitely until either a valid Start bit
occurs or the EUSART is reset.
Work around
When monitoring the RCIDL bit, measure the
length of time between the RCIDL going low and
the RCIF flag going high. If this time is greater than
one character time, then restore the RCIDL bit by
resetting the EUSART receiver. The EUSART
receiver is reset when either the SPEN bit or
CREN bit of the RCSTA register is cleared.
Affected Silicon Revisions
HFINTOSC output frequency may have up to 1%
short term frequency instability beyond the
maximum and minimum limits shown in the data
sheet.
Work around
Use the HS, XT or EC clock modes.
Affected Silicon Revisions
B2
B2
B2
X
X
X
B3
B3
B3
X
X
B5
B5
B5
X
X
9. Module: Data EEPROM Memory
10. Module: Program Flash Memory
11. Module: PORTB Interrupt-on-change
The write/erase endurance of Data EE Memory is
limited to 10K cycles.
Work around
Use the error correction method that stores data in
multiple locations.
Affected Silicon Revisions
The write/erase endurance of the PFM is limited to
1K cycles when V
degrades when V
Work around
For data tables in program Flash memory use the
error correction method that stores data in multiple
locations.
Affected Silicon Revisions
Setting a PORTB interrupt-on-change enable bit of
the IOCB register while the corresponding PORTB
input is high will cause an RBIF interrupt.
Work around
Set the IOCB bits to the desired configuration then
read PORTB to clear the mismatch latches.
Finally, clear the RBIF bit before setting the RBIE
bit.
Affected Silicon Revisions
B2
B2
B2
X
X
X
B3
B3
B3
X
X
X
B5
B5
B5
X
X
X
DD
2010 Microchip Technology Inc.
DD
is below 3V.
is above 3V. Endurance