PIC16F648A-I/SS Microchip Technology, PIC16F648A-I/SS Datasheet - Page 38
![IC MCU FLASH 4KX14 EEPROM 20SSOP](/photos/6/58/65895/150-20-ssop_sml.jpg)
PIC16F648A-I/SS
Manufacturer Part Number
PIC16F648A-I/SS
Description
IC MCU FLASH 4KX14 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 16Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F627A-IP.pdf
(180 pages)
3.PIC16F627A-IP.pdf
(8 pages)
4.PIC16F627A-IP.pdf
(22 pages)
5.PIC16F648A-ISS.pdf
(178 pages)
Specifications of PIC16F648A-I/SS
Core Size
8-Bit
Program Memory Size
7KB (4K x 14)
Core Processor
PIC
Speed
20MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SSOP
Controller Family/series
PIC16F
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
20MHz
No. Of Timers
3
Processor Series
PIC16F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SCI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SS-1 - SOCKET TRANSITION 18DIP 20SSOPI3DBF648 - BOARD DAUGHTER ICEPIC3AC164307 - MODULE SKT FOR PM3 28SSOPAC164018 - MODULE SKT PROMATEII 20SSOP
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F648A-I/SS
Manufacturer:
AD
Quantity:
240
Part Number:
PIC16F648A-I/SS
Manufacturer:
PIC18F14K50-I/SS
Quantity:
20 000
PIC16F627A/628A/648A
5.2
PORTB is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISB. A ‘1’ in
the TRISB register puts the corresponding output driver
in a High-impedance mode. A ‘0’ in the TRISB register
puts the contents of the output latch on the selected
pin(s).
PORTB is multiplexed with the external interrupt,
USART, CCP module and the TMR1 clock input/output.
The standard port functions and the alternate port
functions are shown in Table 5-3. Alternate port
functions may override the TRIS setting when enabled.
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 μA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB<7:4>)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB<7:4>
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
This interrupt can wake the device from Sleep. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression (See Application Note
AN552 “Implementing Wake-up on Key Strokes”
(DS00552).
DS40044G-page 38
Note:
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
PORTB and TRISB Registers
If a change on the I/O pin should occur
when a read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
FIGURE 5-8:
WR PORTB
WR TRISB
RD TRISB
RD PORTB
RBPU
Data Bus
INT
TRIS Latch
Data Latch
D
D
CK
CK
Schmitt
Trigger
Q
Q
Q
Q
BLOCK DIAGRAM OF
RB0/INT PIN
Q
© 2009 Microchip Technology Inc.
EN
EN
D
TTL
Input
Buffer
V
P
DD
Weak Pull-up
V
V
DD
SS
RB0/INT