PIC18F65J11-I/PT Microchip Technology, PIC18F65J11-I/PT Datasheet - Page 128

• Manufacturer Part Number: PIC18F65J11-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 2048Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 52
• Interface Type: I2C/SPI/USART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F85J11 FAMILY
10.6
External interrupts on the RB0/INT0, RB1/INT1,
RB2/INT2 and RB3/INT3 pins are edge-triggered. If the
corresponding INTEDGx bit in the INTCON2 register is
set (= 1), the interrupt is triggered by a rising edge; if
the bit is clear, the trigger is on the falling edge. When
a valid edge appears on the RBx/INTx pin, the
corresponding flag bit, INTxIF, is set. This interrupt can
be disabled by clearing the corresponding enable bit,
INTxIE. Flag bit, INTxIF, must be cleared in software in
the Interrupt Service Routine before re-enabling the
interrupt.
All external interrupts (INT0, INT1, INT2 and INT3) can
wake-up the processor from the power-managed
modes if bit INTxIE was set prior to going into the
power-managed modes. If the Global Interrupt Enable
bit, GIE, is set, the processor will branch to the interrupt
vector following wake-up.
Interrupt priority for INT1, INT2 and INT3 is determined
by the value contained in the interrupt priority bits,
INT1IP (INTCON3<6>), INT2IP (INTCON3<7>) and
INT3IP (INTCON2<1>). There is no priority bit
associated with INT0. It is always a high-priority
interrupt source.
EXAMPLE 10-1:
DS39774D-page 128
MOVWF
MOVFF
MOVFF
;
; USER ISR CODE
;
MOVFF
MOVF
MOVFF
INTx Pin Interrupts
W_TEMP
STATUS, STATUS_TEMP
BSR, BSR_TEMP
BSR_TEMP, BSR
W_TEMP, W
STATUS_TEMP, STATUS
SAVING STATUS, WREG AND BSR REGISTERS IN RAM
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TMEP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
10.7
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh 00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L register
pair (FFFFh 0000h) will set TMR0IF. The interrupt can
be enabled/disabled by setting/clearing enable bit,
TMR0IE (INTCON<5>). Interrupt priority for Timer0 is
determined by the value contained in the interrupt priority
bit, TMR0IP (INTCON2<2>). See Section 12.0 “Timer0
Module” for further details on the Timer0 module.
10.8
An input change on PORTB<7:4> sets flag bit, RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit, RBIE (INTCON<3>).
Interrupt priority for PORTB interrupt-on-change is
determined by the value contained in the interrupt
priority bit, RBIP (INTCON2<0>).
10.9
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the Fast Return Stack. If a fast
return from interrupt is not used (see Section 6.3
“Data Memory Organization”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 10-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
TMR0 Interrupt
PORTB Interrupt-on-Change
Context Saving During Interrupts
 2010 Microchip Technology Inc.