PIC18F65J11-I/PT Microchip Technology, PIC18F65J11-I/PT Datasheet - Page 231

• Manufacturer Part Number: PIC18F65J11-I/PT
• Description: IC PIC MCU FLASH 16KX16 64TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F65J11-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 52
• Ram Memory Size: 2048Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Interface: I2C, SPI, USART
• Package: 64TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 52
• Interface Type: I2C/SPI/USART
• On-chip Adc: 12-chx10-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180018 - MODULE PLUG-IN 18F85J11AC162079 - HEADER MPLAB ICD2 18F85J90 64/80AC164327 - MODULE SKT FOR 64TQFP
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

18.2.3
The Enhanced USART module supports the automatic
detection and calibration of baud rate. This feature is
active only in Asynchronous mode and while the WUE
bit is clear.
The automatic baud rate measurement sequence
(Figure 18-1) begins whenever a Start bit is received
and the ABDEN bit is set. The calculation is
self-averaging.
In the Auto-Baud Rate Detect (ABD) mode, the clock to
the BRG is reversed. Rather than the BRG clocking the
incoming RX1 signal, the RX1 signal is timing the BRG.
In ABD mode, the internal Baud Rate Generator is
used as a counter to time the bit period of the incoming
serial byte stream.
Once the ABDEN bit is set, the state machine will clear
the BRG and look for a Start bit. The Auto-Baud Rate
Detect must receive a byte with the value, 55h (ASCII
“U”, which is also the LIN/J2602 bus Sync character),
in order to calculate the proper bit rate. The measure-
ment is taken over both a low and high bit time in order
to minimize any effects caused by asymmetry of the
incoming signal. After a Start bit, the SPBRG1 begins
counting up, using the preselected clock source on the
first rising edge of RX1. After eight bits on the RX1 pin,
or the fifth rising edge, an accumulated value totalling
the
SPBRGH1:SPBRG1 register pair. Once the 5th edge is
seen (this should correspond to the Stop bit), the
ABDEN bit is automatically cleared.
If a rollover of the BRG occurs (an overflow from FFFFh
to 0000h), the event is trapped by the ABDOVF status bit
(BAUDCON1<7>). It is set in hardware by BRG rollovers
and can be set or cleared by the user in software. ABD
mode remains active after rollover events and the
ABDEN bit remains set (Figure 18-2).
While calibrating the baud rate period, the BRG regis-
ters are clocked at 1/8th the preconfigured clock rate.
Note that the BRG clock can be configured by the
BRG16 and BRGH bits. The BRG16 bit must be set to
use both SPBRG1 and SPBRGH1 as a 16-bit counter.
This allows the user to verify that no carry occurred for
8-bit modes by checking for 00h in the SPBRGH1
register. Refer to Table 18-4 for counter clock rates to
the BRG.
 2010 Microchip Technology Inc.
proper
AUTO-BAUD RATE DETECT
BRG
period
is
left
in
the
PIC18F85J11 FAMILY
While the ABD sequence takes place, the EUSART
state machine is held in Idle. The RC1IF interrupt is set
once the fifth rising edge on RX1 is detected. The value
in the RCREG1 needs to be read to clear the RC1IF
interrupt. The contents of RCREG1 should be
discarded.
TABLE 18-4:
18.2.3.1
Since the BRG clock is reversed during ABD acquisi-
tion, the EUSART transmitter cannot be used during
ABD. This means that whenever the ABDEN bit is set,
TXREG1 cannot be written to. Users should also
ensure that ABDEN does not become set during a
transmit sequence. Failing to do this may result in
unpredictable EUSART operation.
BRG16
Note:
Note 1: If the WUE bit is set with the ABDEN bit,
0
0
1
1
2: It is up to the user to determine that the
BRGH
During the ABD sequence, SPBRG1 and
SPBRGH1 are both used as a 16-bit
counter, independent of the BRG16 setting.
Auto-Baud Rate Detection will occur on
the byte following the Break character.
incoming character baud rate is within the
range of the selected BRG clock source.
Some combinations of oscillator frequency
and EUSART baud rates are not possible
due to bit error rates. Overall system
timing and communication baud rates
must be taken into consideration when
using the Auto-Baud Rate Detection
feature.
ABD and EUSART Transmission
0
1
0
1
BRG COUNTER CLOCK
RATES
BRG Counter Clock
F
F
F
F
OSC
OSC
OSC
OSC
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