ATMEGA8L-8MU Atmel, ATMEGA8L-8MU Datasheet - Page 227

• Manufacturer Part Number: ATMEGA8L-8MU
• Description: IC AVR MCU 8K 8MHZ 3V 32-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA8L-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 23
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Package: 32MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 23
• Interface Type: SPI/TWI/USART
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Controller Family/series: AVR MEGA
• No. Of I/o's: 23
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reading the Signature
Bytes
Reading the
Calibration Byte
Parallel Programming
Characteristics
2486Z–AVR–02/11
The algorithm for reading the Signature bytes is as follows (refer to
page 222
1. A: Load Command “0000 1000”
2. B: Load Address Low byte (0x00 - 0x02)
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”
The algorithm for reading the Calibration bytes is as follows (refer to
page 222
1. A: Load Command “0000 1000”
2. B: Load Address Low byte, (0x00 - 0x03)
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA
4. Set OE to “1”
Figure 109. Parallel Programming Timing, Including some General Timing Requirements
Figure 110. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
(DATA, XA0/1, BS1, BS2)
PAGEL
XTAL1
DATA
BS1
XA0
XA1
1. The timing requirements shown in
for details on Command and Address loading):
for details on Command and Address loading):
loading operation
Data & Contol
RDY/BSY
ADDR0 (Low Byte)
LOAD ADDRESS
PAGEL
XTAL1
(LOW BYTE)
WR
t
t
BVPH
DVXH
LOAD DATA
(LOW BYTE)
DATA (Low Byte)
t
t
XHXL
PHPL
Figure 109
t
t
t
t
t
XLXH
XLDX
PLBX
XLWL
PLWL
t
(that is, t
BVWL
(HIGH BYTE)
LOAD DATA
DATA (High Byte)
t
WL WH
t
XLPH
WLRL
DVXH
LOAD DATA
, t
“Programming the Flash” on
“Programming the Flash” on
XHXL
t
PLXH
t
, and t
ATmega8(L)
WLBX
LOAD ADDRESS
(LOW BYTE)
XLDX
ADDR1 (Low Byte)
) also apply to
t
WLRH
(1)
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