PIC24FJ16GA004-E/PT Microchip Technology, PIC24FJ16GA004-E/PT Datasheet - Page 15

• Manufacturer Part Number: PIC24FJ16GA004-E/PT
• Description: IC PIC MCU FLASH 16K 44-TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ16GA004-E/PT

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 4 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, MA240013, AC164127, DM300027, DV164033, DM240002
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARDDM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164335 - MODULE SKT FOR 10X10 PM3 44TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

43. Module: SPI
44. Module: UART (IrDA
 2010 Microchip Technology Inc.
SPI operating in Enhanced Buffer mode
(SPIBEN = 1) may set the interrupt flag, SPIxIF,
before the last bit has been transmitted from the
shift register. This issue only affects one of the
eight Interrupt modes, SISEL<2:0> = 101,
which generates an interrupt when the last bit
has shifted out of the shift register, indicating the
transfer is complete. All other Interrupt modes in
Enhanced Buffer mode work as described in the
product data sheet.
Work around
Multiple work arounds are available. Select
another Buffer Interrupt mode using the
SISEL<2:0> bits in the SPIxSTAT register. A
comparable mode is to generate an interrupt
when the FIFO is empty, SISEL<2:0> = 110.
Another option is to monitor the SRMPT bit
(SPIxSTAT<7>) to determine when the shift
register is empty.
Affected Silicon Revisions
When
(UxMODE<12> = 1), the operation of the
RXINV bit (UxMODE<4>) is the opposite of its
description in the device data sheet (DS39881);
that is, setting the bit configures the module for
a logic high Idle state, and clearing the bit
configures the module for a logic low Idle state.
Using the bit as described in the data sheet may
result in reception errors.
Work around
Invert the state of the RXINV bit. If the Idle state of
the received signal is logic high, set RXINV = 1. If
the Idle state of the received signal is logic low,
clear RXINV.
Affected Silicon Revisions
A3/
A3/
A4
A4
X
X
B4
B4
X
IrDA
B5
B5
X
reception
B8
B8
X
®
)
is
enabled
PIC24FJ64GA004 FAMILY
45. Module: Core
46. Module: SPI (Master Mode)
Operations that immediately follow any manipula-
tions of the DOZE<2:0> or DOZEN bits
(CLKDIV<14:11>) may not execute properly. In
particular, for instructions that operate on an
SFR, data may not be read properly. Also, bits
automatically cleared in hardware may not be
cleared if the operation occurs during this interval.
Work around
Always insert a NOP instruction before and after
either of the following:
•
•
Affected Silicon Revisions
When operating in Enhanced Buffer Master mode,
the module may transmit two bytes or two words of
data with a value of 0h, immediately upon the
microcontroller waking up from Sleep mode. At the
same time, the module “receives” two words or two
bytes of data, also with the value of 0h.
The transmission of null data occurs even if the
Transmit Buffer registers are empty prior to the
microcontroller
received null data requires that the receive buffer
be read twice to clear the “received” data.
This behavior has not been observed when the
module is operating in any other mode.
Work around
When operating in Enhanced Buffer Master mode,
disable the module (SPIEN = 0) before entering
Sleep mode.
Affected Silicon Revisions
A3/
A3/
A4
A4
X
X
Enabling or disabling Doze mode by setting
or clearing the DOZEN bit.
Before or after changing the DOZE<2:0>
bits.
B4
B4
X
X
B5
B5
X
X
entering
B8
B8
X
X
Sleep
DS80470E-page 15
mode.
The