PIC24FJ16GA MICROCHIP [Microchip Technology], PIC24FJ16GA Datasheet
PIC24FJ16GA
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PIC24FJ16GA Summary of contents
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PIC24FJ64GA004 Family © 2008 Microchip Technology Inc. Data Sheet 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers Preliminary DS39881C ...
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families ...
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General Purpose, 16-Bit Flash Microcontrollers High-Performance CPU: • Modified Harvard Architecture • MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options • 17-Bit by 17-Bit Single-Cycle Hardware ...
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PIC24FJ64GA004 FAMILY Pin Diagrams 28-Pin SPDIP, SSOP, SOIC AN0/V REF AN1/V REF PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 SOSCI/RP4/PMBE/CN1/RB4 SOSCO/T1CK/CN0/PMA1/RA4 PGD3/EMUD3/RP5/ASDA1/CN27/PMD7/RB5 (1) 28-Pin QFN PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 Legend: RPn represents remappable peripheral pins. Note 1: Back pad ...
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Pin Diagrams (Continued) (1) 44-Pin QFN RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG V CAP PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 Legend: RPn represents remappable peripheral pins. Note 1: Back pad on QFN devices should be connected to Vss. © 2008 Microchip Technology ...
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PIC24FJ64GA004 FAMILY Pin Diagrams (Continued) 44-Pin TQFP RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG V /V CAP DDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 Legend: RPn represents remappable peripheral pins. DS39881C-page SOSCI/RP4/CN1/RB4 32 TDO/PMA8/RA8 2 31 OSCO/CLKO/CN29/RA3 3 30 OSCI/CLKI/CN30/RA2 ...
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Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU ........................................................................................................................................................................................... 17 3.0 Memory Organization ................................................................................................................................................................. 23 4.0 Flash Program Memory.............................................................................................................................................................. 41 5.0 Resets ........................................................................................................................................................................................ 47 6.0 Interrupt Controller ..................................................................................................................................................................... 53 7.0 Oscillator Configuration .............................................................................................................................................................. 87 8.0 Power-Saving Features.............................................................................................................................................................. 95 ...
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PIC24FJ64GA004 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better ...
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... This document contains device-specific information for the following devices: • PIC24FJ16GA002 • PIC24FJ32GA002 • PIC24FJ48GA002 • PIC24FJ64GA002 • PIC24FJ16GA004 • PIC24FJ32GA004 • PIC24FJ48GA004 • PIC24FJ64GA004 This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. ...
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... PIC24FJ64GA PIC24FJ48GA PIC24FJ32GA devices and 16 Kbytes for PIC24FJ16GA devices). 2. Internal SRAM memory (4k for PIC24FJ16GA devices, 8k for all other devices in the family). 3. Available I/O pins and ports (21 pins on 2 ports for 28-pin devices and 35 pins on 3 ports for 44-pin devices). All other features for devices in this family are identical. ...
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TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input ...
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PIC24FJ64GA004 FAMILY FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller PSV & Table Data Access Control Block 23 23 Address Latch Program Memory Data Latch Address Bus Instruction Decode & Control Power-up Timing OSCO/CLKO Timer Generation OSCI/CLKI Oscillator Start-up ...
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC AN0 2 27 AN1 3 28 AN2 4 1 AN3 5 2 AN4 6 3 AN5 7 4 AN6 — — AN7 — — AN8 ...
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PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC CN0 12 9 CN1 11 8 CN2 2 27 CN3 3 28 CN4 4 1 CN5 5 2 CN6 6 3 CN7 ...
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC OSCI 9 6 OSCO 10 7 PGC1 5 2 PGD1 4 1 PGC2 22 19 PGD2 21 18 PGC3 14 12 PGD3 15 11 ...
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PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC RA0 2 27 RA1 3 28 RA2 9 6 RA3 10 7 RA4 12 9 RA7 — — RA8 — — RA9 ...
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC RP0 4 1 RP1 5 2 RP2 6 3 RP3 7 4 RP4 11 8 RP5 14 11 RP6 15 12 RP7 16 13 ...
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PIC24FJ64GA004 FAMILY TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 28-Pin Function 28-Pin SPDIP/ QFN QFN/TQFP SSOP/SOIC T1CK 12 9 TCK 17 14 TDI 21 18 TDO 18 15 TMS 13 ...
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CPU Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 2. CPU” (DS39703). The PIC24F ...
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PIC24FJ64GA004 FAMILY FIGURE 2-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & ...
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TABLE 2-1: CPU CORE REGISTERS Register(s) Name W0 through W15 PC SR SPLIM TBLPAG PSVPAG RCOUNT CORCON FIGURE 2-2: PROGRAMMER’S MODEL W0 (WREG) Divider Working Registers W1 W2 Multiplier Registers W10 W11 W12 ...
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PIC24FJ64GA004 FAMILY 2.2 CPU Control Registers REGISTER 2-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (1) R/W-0 R/W-0 R/W-0 (2) (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W = ...
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REGISTER 2-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is ...
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PIC24FJ64GA004 FAMILY 2.3.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit ...
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... The program address memory PIC24FJ64GA004 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES PIC24FJ16GA PIC24FJ32GA GOTO Instruction GOTO Instruction Reset Address Reset Address Interrupt Vector Table Interrupt Vector Table ...
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... Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 23.1 “Configuration Bits”. TABLE 3-1: Device PIC24FJ16GA PIC24FJ32GA PIC24FJ48GA PIC24FJ64GA least significant word ...
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... FFFFh Note 1: Data memory areas are not shown to scale. 2: Upper memory limit for PIC24FJ16GAXXX devices is 17FFh. © 2008 Microchip Technology Inc. PIC24FJ64GA004 FAMILY PIC24FJ64GA family devices implement a total of 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned ...
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PIC24FJ64GA004 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations consequence of byte accessibility, all Effective Address ...
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Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 27 ...
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PIC24FJ64GA004 FAMILY DS39881C-page 28 Preliminary © 2008 Microchip Technology Inc. ...
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Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 29 ...
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PIC24FJ64GA004 FAMILY DS39881C-page 30 Preliminary © 2008 Microchip Technology Inc. ...
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Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 31 ...
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PIC24FJ64GA004 FAMILY DS39881C-page 32 Preliminary © 2008 Microchip Technology Inc. ...
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Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 33 ...
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PIC24FJ64GA004 FAMILY DS39881C-page 34 Preliminary © 2008 Microchip Technology Inc. ...
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Microchip Technology Inc. PIC24FJ64GA004 FAMILY Preliminary DS39881C-page 35 ...
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PIC24FJ64GA004 FAMILY DS39881C-page 36 Preliminary © 2008 Microchip Technology Inc. ...
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SOFTWARE STACK In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower ...
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PIC24FJ64GA004 FAMILY TABLE 3-25: PROGRAM SPACE ADDRESS CONSTRUCTION Access Access Type Space Instruction Access User (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) Configuration Program Space Visibility User (Block Remap/Read) Note 1: Data EA<15> is always ‘1’ in this case, but is ...
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DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and ...
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PIC24FJ64GA004 FAMILY 3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data ...
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FLASH PROGRAM MEMORY Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 4. Program (DS39715). ...
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PIC24FJ64GA004 FAMILY 4.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions time and to program one ...
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REGISTER 4-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0 R/W-0 R/W-0 WR WREN WRERR bit 15 U-0 R/W-0 U-0 — ERASE — bit 7 Legend Set Only bit R = Readable bit W = Writable bit -n = Value ...
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PIC24FJ64GA004 FAMILY 4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY The user can program one row of Flash program memory at a time this necessary to erase the 8-row erase block containing the desired row. The general ...
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EXAMPLE 4-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes ...
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PIC24FJ64GA004 FAMILY 4.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be pro- grammed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register ...
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RESETS Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 7. Reset” (DS39712). The Reset ...
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PIC24FJ64GA004 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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TABLE 5-1: RESET FLAG BIT OPERATION Flag Bit TRAPR (RCON<15>) Trap Conflict Event IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access CM (RCON<9>) Configuration Mismatch Reset EXTR (RCON<7>) MCLR Reset SWR (RCON<6>) RESET Instruction WDTO (RCON<4>) WDT Time-out SLEEP ...
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PIC24FJ64GA004 FAMILY TABLE 5-3: RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Reset Type Clock Source POR EC, FRC, FRCDIV, LPRC T ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL BOR EC, FRC, FRCDIV, LPRC ECPLL, FRCPLL XT, HS, SOSC XTPLL, HSPLL ...
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POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up ...
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PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 52 Preliminary © 2008 Microchip Technology Inc. ...
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INTERRUPT CONTROLLER Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 8. Interrupts” (DS39707). The ...
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PIC24FJ64GA004 FAMILY FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt ...
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TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source ADC1 Conversion Done Comparator Event CRC Generator External Interrupt 0 External Interrupt 1 External Interrupt 2 I2C1 Master Event I2C1 Slave Event I2C2 Master Event I2C2 Slave Event Input Capture 1 Input Capture ...
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PIC24FJ64GA004 FAMILY 6.3 Interrupt Control and Status Registers The PIC24FJ64GA004 family of devices implements a total of 28 registers for the interrupt controller: • INTCON1 • INTCON2 • IFS0 through IFS4 • IEC0 through IEC4 • IPC0 through IPC12, IPC15, ...
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REGISTER 6-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (2,3) (2,3) (2,3) IPL2 IPL1 IPL0 bit 7 Legend Readable bit W = Writable bit -n = Value at ...
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PIC24FJ64GA004 FAMILY REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
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REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 ALTIVT DISI — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit ...
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PIC24FJ64GA004 FAMILY REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIF U2RXIF INT2IF bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 — — PMPIF bit 15 R/W-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 U-0 — RTCIF — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 U2TXIE U2RXIE INT2IE bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 — — PMPIE bit 15 R/W-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 — RTCIE — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP2 T1IP1 bit 15 U-0 R/W-1 R/W-0 — IC1IP2 IC1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 — T2IP2 T2IP1 bit 15 U-0 R/W-1 R/W-0 — IC2IP2 IC2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP2 U1RXIP1 bit 15 U-0 R/W-1 R/W-0 — SPF1IP2 SPF1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — AD1IP2 AD1IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP2 CNIP1 bit 15 U-0 R/W-1 R/W-0 — MI2C1P2 MI2C1P1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 — T4IP2 T4IP1 bit 15 U-0 R/W-1 R/W-0 — OC3IP2 OC3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 — U2TXIP2 U2TXIP1 bit 15 U-0 R/W-1 R/W-0 — INT2IP2 INT2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SPI2IP2 SPI2IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 — IC5IP2 IC5IP1 bit 15 U-0 R/W-1 R/W-0 — IC3IP2 IC3IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-25: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — OC5IP2 OC5IP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-27: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — SI2C2P2 SI2C2P1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-28: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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REGISTER 6-29: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 — CRCIP2 CRCIP1 bit 15 U-0 R/W-1 R/W-0 — U1ERIP2 U1ERIP1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
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PIC24FJ64GA004 FAMILY REGISTER 6-30: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
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Interrupt Setup Procedures 6.4.1 INITIALIZATION To configure an interrupt source: 1. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. 2. Select the user-assigned priority level for the interrupt source by writing the control bits in ...
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PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 86 Preliminary © 2008 Microchip Technology Inc. ...
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OSCILLATOR CONFIGURATION Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 6. Oscillator” (DS39700). The ...
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PIC24FJ64GA004 FAMILY 7.1 CPU Clocking Scheme The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast ...
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Control Registers The operation of the oscillator is controlled by three Special Function Registers: • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 7-1) is the main con- trol register for the oscillator. It controls clock source switching ...
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PIC24FJ64GA004 FAMILY REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1 Clock and PLL selections are locked 0 = Clock and PLL selections are not ...
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REGISTER 7-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 bit 15 U-0 U-1 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is ...
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PIC24FJ64GA004 FAMILY REGISTER 7-3: OSCTUN: FRC Oscillator Tune Register U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — TUN5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
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OSCILLATOR SWITCHING SEQUENCE At a minimum, performing a clock switch requires this basic sequence desired, read the COSCx (OSCCON<14:12>), to determine the current oscillator source. 2. Perform the unlock sequence to allow a write to the OSCCON ...
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PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 94 Preliminary © 2008 Microchip Technology Inc. ...
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POWER-SAVING FEATURES Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 10. Power-Saving Features” (DS39698). ...
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PIC24FJ64GA004 FAMILY 8.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from ...
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I/O PORTS Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 12. I/O Ports with ...
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PIC24FJ64GA004 FAMILY 9.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually con- figured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ...
Page 101
Peripheral Pin Select A major challenge in general purpose devices is provid- ing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The chal- lenge is even greater on low pin count ...
Page 102
PIC24FJ64GA004 FAMILY TABLE 9-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer2 External Clock Timer3 External Clock Timer4 External Clock Timer5 External Clock Input Capture 1 Input Capture 2 Input Capture 3 ...
Page 103
TABLE 9-2: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Function Output Name (1) Number (2) NULL 0 NULL C1OUT 1 Comparator 1 Output C2OUT 2 Comparator 2 Output U1TX 3 UART1 Transmit (3) U1RTS 4 UART1 Request To ...
Page 104
PIC24FJ64GA004 FAMILY 9.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. ...
Page 105
Peripheral Pin Select Registers The PIC24FJ64GA004 family of devices implements a total of 27 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (14) • Output Remappable Peripheral Registers (13) REGISTER 9-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER ...
Page 106
PIC24FJ64GA004 FAMILY REGISTER 9-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 107
REGISTER 9-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 108
PIC24FJ64GA004 FAMILY REGISTER 9-7: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 109
REGISTER 9-9: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 110
PIC24FJ64GA004 FAMILY REGISTER 9-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 111
REGISTER 9-13: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 112
PIC24FJ64GA004 FAMILY REGISTER 9-15: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 113
REGISTER 9-17: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 114
PIC24FJ64GA004 FAMILY REGISTER 9-19: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 115
REGISTER 9-21: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 116
PIC24FJ64GA004 FAMILY REGISTER 9-23: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 117
REGISTER 9-25: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 118
PIC24FJ64GA004 FAMILY REGISTER 9-27: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 119
TIMER1 Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 14. Timers” (DS39704). The Timer1 ...
Page 120
PIC24FJ64GA004 FAMILY REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
Page 121
TIMER2/3 AND TIMER4/5 Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 14. Timers” (DS39704). ...
Page 122
PIC24FJ64GA004 FAMILY FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T3IF (T5IF) 0 (3) ADC Event Trigger Equal MSB Reset (1) Read TMR2 (TMR4) (1) Write TMR2 (TMR4) Data Bus<15:0> Note 1: The 32-Bit Timer ...
Page 123
FIGURE 11-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T2CK (T4CK) TGATE 1 Set T2IF (T4IF) 0 Reset Equal Note 1: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin ...
Page 124
PIC24FJ64GA004 FAMILY REGISTER 11-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
Page 125
REGISTER 11-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER R/W-0 U-0 R/W-0 (1) TON — TSIDL bit 15 U-0 R/W-0 R/W-0 (1) — TGATE TCKPS1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...
Page 126
PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 124 Preliminary © 2008 Microchip Technology Inc. ...
Page 127
INPUT CAPTURE Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 15. Input Capture” (DS39701). ...
Page 128
PIC24FJ64GA004 FAMILY 12.1 Input Capture Registers REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI1 ICI0 bit 7 Legend Hardware Clearable bit R = Readable bit ...
Page 129
OUTPUT COMPARE Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 16. Output (DS39706). 13.1 ...
Page 130
PIC24FJ64GA004 FAMILY 13.3 Pulse-Width Modulation Mode Note: This peripheral contains input and output functions that may need to be configured by the peripheral pin Section 9.4 “Peripheral Pin Select” for more information. The following steps should be taken when configuring ...
Page 131
EXAMPLE 13-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS 1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where F (32 MHz device clock rate) and a Timer2 prescaler setting of 1: ...
Page 132
PIC24FJ64GA004 FAMILY FIGURE 13-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM (1) OCxRS (1) OCxR Comparator OCTSEL TMR register inputs from time bases (see Note 3). Note 1: Where ‘x’ is shown, reference is made to the registers ...
Page 133
Output Compare Register REGISTER 13-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER U-0 U-0 R/W-0 — — OCSIDL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Hardware Clearable bit R = Readable bit W = ...
Page 134
PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 132 Preliminary © 2008 Microchip Technology Inc. ...
Page 135
SERIAL PERIPHERAL INTERFACE (SPI) Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 23. Serial ...
Page 136
PIC24FJ64GA004 FAMILY To set up the SPI module for the Standard Master mode of operation using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) ...
Page 137
To set up the SPI module for the Enhanced Buffer Master mode of operation using interrupts: a) Clear the SPIxIF bit in the respective IFSx register. b) Set the SPIxIE bit in the respective IECx register. c) Write ...
Page 138
PIC24FJ64GA004 FAMILY REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 (1) SPIEN — SPISIDL bit 15 R-0 R/C-0 R/W-0 SRMPT SPIROV SRXMPT bit 7 Legend Clearable bit R = Readable bit W = Writable bit ...
Page 139
REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set ...
Page 140
PIC24FJ64GA004 FAMILY REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 (4) SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value ...
Page 141
REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 (CONTINUED) X bit 4-2 SPRE2:SPRE0: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 bit 1-0 PPRE1:PPRE0: Primary Prescale bits ...
Page 142
PIC24FJ64GA004 FAMILY FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) Serial Receive Buffer (2) (SPIxRXB) Shift Register (SPIxSR) MSb Serial Transmit Buffer (2) (SPIxTXB) SPIx Buffer (2) (SPIxBUF) MSTEN (SPIxCON1<5> Note 1: Using the SSx ...
Page 143
FIGURE 14-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE 14-6: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24F SPI Master, Frame Slave) FIGURE 14-7: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24F (SPI Slave, Frame Slave) FIGURE ...
Page 144
PIC24FJ64GA004 FAMILY EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK Note 1: Based TABLE 14-1: SAMPLE SCK FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary ...
Page 145
INTER-INTEGRATED CIRCUIT 2 (I C™) Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 24. ...
Page 146
PIC24FJ64GA004 FAMILY 2 FIGURE 15-1: I C™ BLOCK DIAGRAM Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS39881C-page 144 I2CxRCV I2CxRSR LSB Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect ...
Page 147
Setting Baud Rate When Operating as a Bus Master To compute the Baud Rate Generator reload value, use Equation 15-1. EQUATION 15-1: COMPUTING BAUD RATE RELOAD VALUE --------------------------------------------------------------------- - SCL F I2CxBRG + + 1 ...
Page 148
PIC24FJ64GA004 FAMILY REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 I2CEN — I2CSIDL bit 15 R/W-0 R/W-0 R/W-0 GCEN STREN ACKDT bit 7 Legend Hardware Clearable bit R = Readable bit W = Writable bit -n = ...
Page 149
REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (When operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Sends NACK during Acknowledge 0 = Sends ACK during ...
Page 150
PIC24FJ64GA004 FAMILY REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 ACKSTAT TRSTAT — bit 15 R/C-0, HS R/C-0, HS R-0, HSC IWCOL I2COV D/A bit 7 Legend Clearable bit R = Readable bit W = ...
Page 151
REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or ...
Page 152
PIC24FJ64GA004 FAMILY REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 153
UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 21. ...
Page 154
PIC24FJ64GA004 FAMILY 16.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate ...
Page 155
Transmitting in 8-Bit Data Mode 1. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and ...
Page 156
PIC24FJ64GA004 FAMILY REGISTER 16-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 (1) UARTEN — USIDL bit 15 R/C-0, HC R/W-0 R/W-0, HC WAKE LPBACK ABAUD bit 7 Legend Clearable bit R = Readable bit W = Writable bit ...
Page 157
REGISTER 16-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates ...
Page 158
PIC24FJ64GA004 FAMILY REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL1 URXISEL0 ADDEN bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n ...
Page 159
REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. ...
Page 160
PIC24FJ64GA004 FAMILY REGISTER 16-3: UxTXREG: UARTx TRANSMIT REGISTER U-x U-x U-x — — — bit 15 W-x W-x W-x UTX7 UTX6 UTX5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
Page 161
PARALLEL MASTER PORT (PMP) Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 13. Parallel ...
Page 162
PIC24FJ64GA004 FAMILY REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 PMPEN — PSIDL bit 15 R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 163
REGISTER 17-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master Mode ...
Page 164
PIC24FJ64GA004 FAMILY REGISTER 17-2: PMMODE: Parallel Port Mode Register R-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 bit 15 R/W-0 R/W-0 R/W-0 (1) (1) WAITB1 WAITB0 WAITM3 bit 7 Legend Readable bit W = Writable bit -n = Value at ...
Page 165
REGISTER 17-3: PMADDR: PARALLEL PORT ADDRESS REGISTER U-0 R/W-0 U-0 — CS1 — bit 15 R/W-0 R/W-0 R/W-0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit ...
Page 166
PIC24FJ64GA004 FAMILY REGISTER 17-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 IBF IBOV — bit 15 R-1 R/W-0, HS U-0 OBE OBUF — bit 7 Legend Hardware Set bit R = Readable bit W = Writable ...
Page 167
REGISTER 17-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit ...
Page 168
PIC24FJ64GA004 FAMILY FIGURE 17-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PMD<7:0> PMCS1 PMRD PMWR FIGURE 17-3: ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PMA<1:0> PMD<7:0> PMCS1 PMRD PMWR Address Bus Data Bus Control Lines TABLE 17-1: SLAVE MODE ADDRESS RESOLUTION PMA<1:0> ...
Page 169
FIGURE 17-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT) PIC24F FIGURE 17-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT) PIC24F FIGURE 17-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION ...
Page 170
PIC24FJ64GA004 FAMILY FIGURE 17-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F PMD<7:0> PMALL PMCS1 PMRD PMWR FIGURE 17-10: PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA) PIC24F PMA<n:0> PMD<7:0> PMCS1 PMRD PMWR FIGURE 17-11: PARALLEL EEPROM ...
Page 171
REAL-TIME CLOCK AND CALENDAR (RTCC) Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 29. ...
Page 172
PIC24FJ64GA004 FAMILY 18.1 RTCC Module Registers The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 18.1.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm ...
Page 173
RTCC CONTROL REGISTERS REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER R/W-0 U-0 R/W-0 (2) RTCEN — RTCWREN bit 15 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 bit 7 Legend Readable bit W = Writable bit -n = ...
Page 174
PIC24FJ64GA004 FAMILY REGISTER 18-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER bit 7-0 CAL7:CAL0: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 01111111 = Minimum positive adjustment; adds 4 RTC clock ...
Page 175
REGISTER 18-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 bit 15 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is ...
Page 176
PIC24FJ64GA004 FAMILY 18.1.4 RTCVAL REGISTER MAPPINGS REGISTER 18-4: YEAR: YEAR VALUE REGISTER U-0 U-0 U-0 — — — bit 15 R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value ...
Page 177
REGISTER 18-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-x — — HRTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
Page 178
PIC24FJ64GA004 FAMILY 18.1.5 ALRMVAL REGISTER MAPPINGS REGISTER 18-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-x — — DAYTEN1 bit 7 Legend Readable bit W = Writable bit ...
Page 179
REGISTER 18-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x — MINTEN2 MINTEN1 bit 15 U-0 R/W-x R/W-x — SECTEN2 SECTEN1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 180
PIC24FJ64GA004 FAMILY 18.3 Alarm • Configurable from half second to one year • Enabled using the ALRMEN bit (ALCFGRPT<15>, Register 18-3) • One-time alarm and repeat alarm options available 18.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ...
Page 181
PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section ...
Page 182
PIC24FJ64GA004 FAMILY FIGURE 19-2: CRC GENERATOR RECONFIGURED FOR x XOR SDOx BIT 0 BIT 4 p_clk p_clk 19.1 User Interface 19.1.1 DATA INTERFACE To start serial shifting, a ‘1’ must be written to the CRCGO bit. ...
Page 183
Registers There are four registers used to control programmable CRC operation: • CRCCON • CRCXOR • CRCDAT • CRCWDAT REGISTER 19-1: CRCCON: CRC CONTROL REGISTER U-0 U-0 R/W-0 — — CSIDL bit 15 R-0 R-1 U-0 CRCFUL CRCMPT — ...
Page 184
PIC24FJ64GA004 FAMILY REGISTER 19-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 X15 X14 X13 bit 15 R/W-0 R/W-0 R/W bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 185
HIGH-SPEED A/D CONVERTER Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 17. 10-Bit ...
Page 186
PIC24FJ64GA004 FAMILY FIGURE 20-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM REF REF AN0 V INH AN1 AN2 AN3 AN4 V INL AN5 (1) AN6 (1) AN7 ...
Page 187
REGISTER 20-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/C-0 ADON — ADSIDL bit 15 R/W-0 R/W-0 R/W-0 SSRC2 SSRC1 SSRC0 bit 7 Legend Clearable bit R = Readable bit W = Writable bit -n = Value at ...
Page 188
PIC24FJ64GA004 FAMILY REGISTER 20-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 VCFG2 VCFG1 VCFG0 bit 15 R-0 U-0 R/W-0 BUFS — SMPI3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 189
REGISTER 20-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 U-0 U-0 ADRC — — bit 15 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit ...
Page 190
PIC24FJ64GA004 FAMILY REGISTER 20-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 CH0NB — — bit 15 R/W-0 U-0 U-0 CH0NA — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 191
REGISTER 20-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER R/W-0 U-0 U-0 PCFG15 — — bit 15 R/W-0 R/W-0 R/W-0 (1) (1) PCFG7 PCFG6 PCFG5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ ...
Page 192
PIC24FJ64GA004 FAMILY EQUATION 20-1: A/D CONVERSION CLOCK PERIOD Note 1: Based on T FIGURE 20-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL ANx PIN 6-11 pF (Typical) Legend: C Note: C value depends on device package and is ...
Page 193
FIGURE 20-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 ...
Page 194
PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 192 Preliminary © 2008 Microchip Technology Inc. ...
Page 195
COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 16. Output (DS39706). FIGURE ...
Page 196
PIC24FJ64GA004 FAMILY REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER R/W-0 U-0 R/C-0 CMIDL — C2EVT bit 15 R-0 R-0 R/W-0 C2OUT C1OUT C2INV bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = ...
Page 197
REGISTER 21-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED) bit 5 C2INV: Comparator 2 Output Inversion bit output inverted output not inverted bit 4 C1INV: Comparator 1 Output Inversion bit output inverted 0 ...
Page 198
PIC24FJ64GA004 FAMILY NOTES: DS39881C-page 196 Preliminary © 2008 Microchip Technology Inc. ...
Page 199
COMPARATOR VOLTAGE REFERENCE Note: This data sheet summarizes the features of this group of PIC24F devices not intended comprehensive reference source. For more information, refer to the “PIC24F Family Reference ”Section 20. Comparator Voltage ...
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PIC24FJ64GA004 FAMILY REGISTER 22-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR bit 7 Legend Readable bit W = Writable bit -n = Value at POR ...