PIC24FJ16GA MICROCHIP [Microchip Technology], PIC24FJ16GA Datasheet - Page 45

• Manufacturer Part Number: PIC24FJ16GA
• Description: 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
• Manufacturer: MICROCHIP [Microchip Technology]

REGISTER 4-1:
© 2008 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
Note 1:
R/SO-0
WR
U-0
—
2:
All other combinations of NVMOP3:NVMOP0 are unimplemented.
Available in ICSP™ mode only. Refer to device programming specification.
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enable Flash program/erase operations
0 = Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt or termination has occurred (bit is set
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command
0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command
Unimplemented: Read as ‘0’
NVMOP3:NVMOP0: NVM Operation Select bits
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
ERASE
WREN
R/W-0
R/W-0
cleared by hardware once operation is complete.
automatically on any set attempt of the WR bit)
NVMCON: FLASH MEMORY CONTROL REGISTER
SO = Set Only bit
W = Writable bit
‘1’ = Bit is set
WRERR
R/W-0
U-0
—
U-0
U-0
PIC24FJ64GA004 FAMILY
—
—
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NVMOP3
R/W-0
(1)
U-0
—
(1)
NVMOP2
R/W-0
U-0
—
(1)
x = Bit is unknown
NVMOP1
R/W-0
U-0
—
(2)
(1)
DS39881C-page 43
NVMOP0
R/W-0
U-0
—
bit 8
bit 0
(1)