PIC24HJ12GP201-I/P Microchip Technology, PIC24HJ12GP201-I/P Datasheet - Page 3
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PIC24HJ12GP201-I/P
Manufacturer Part Number
PIC24HJ12GP201-I/P
Description
IC PIC MCU FLASH 4KX24 18DIP
Manufacturer
Microchip Technology
Series
PIC® 24Hr
Datasheets
1.PIC24HJ12GP201-ISO.pdf
(242 pages)
2.PIC24HJ12GP201-ISO.pdf
(8 pages)
3.PIC24HJ12GP201-ISO.pdf
(84 pages)
4.PIC24HJ12GP201-ISO.pdf
(12 pages)
5.PIC24HJ12GP201-IP.pdf
(234 pages)
Specifications of PIC24HJ12GP201-I/P
Program Memory Type
FLASH
Program Memory Size
12KB (4K x 24)
Package / Case
18-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 6x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC24HJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
1 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
13
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit or 6-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164337 - MODULE SOCKET FOR PM3 40DIP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Module
UART
CPU
ADC
SPI
I
I
I
2
2
2
C
C
C
Only those issues indicated in the last column apply to the current silicon revision.
Consumption
Addressing
Generation
Instruction
Character
FRMDLY
SILICON ISSUE SUMMARY (CONTINUED)
Feature
in Sleep
Current
Break
10-bit
Slave
Mode
EXCH
—
—
Number
Item
19.
20.
21.
22.
23.
24.
25.
With the I
interrupt input functions (if any) associated with SCL and
SDA pins do not reflect the actual digital logic levels on the
pins.
The 10-bit slave does not set the RBF flag or load the
I2CxRCV register on address match if the Least Significant
bits (LSbs) of the address are the same as the 7-bit
reserved addresses.
After the ACKSTAT bit is set when receiving a NACK, it
may be cleared by the reception of a Start or Stop bit.
The EXCH instruction does not execute correctly.
The UART module will not generate back-to-back Break
characters.
The SPI communication in Framed mode does not function
correctly if the Slave SPI frame delay bit (FRMDLY) is set
to ‘1’.
If the ADC module is in an enabled state when the device
enters Sleep Mode, the power-down current (I
device may exceed the device data sheet specifications.
2
C module enabled, the port bits and external
Issue Summary
PD
) of the
A2 A3 A4 A5
X
X
X
X
X
X
X
DS80466E-page 3
Revisions
Affected
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
X
X
X
X
X
X
X