PIC24HJ12GP201-I/P Microchip Technology, PIC24HJ12GP201-I/P Datasheet
PIC24HJ12GP201-I/P
Specifications of PIC24HJ12GP201-I/P
Related parts for PIC24HJ12GP201-I/P
PIC24HJ12GP201-I/P Summary of contents
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... Microchip Technology Inc. PIC24HJ12GP201/202 High-Performance, 16-Bit Microcontrollers Preliminary Data Sheet DS70282B ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... On-Chip Flash and SRAM: • Flash program memory (12 Kbytes) • Data SRAM (1024 bytes) • Boot and General Security for Program Flash © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Digital I/O: • Peripheral Pin Select Functionality • programmable digital I/O pins • Wake-up/Interrupt-on-Change for pins • ...
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... PIC24HJ12GP201/202 Communication Modules: • 4-wire SPI: - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes 2 • I C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration ...
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... PIC24HJ12GP201/202 Product Families The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ12GP201/202 CONTROLLER FAMILIES Device PIC24HJ12GP201 18 12 PIC24HJ12GP202 28 12 Note 1: Only 2 out of 3 timers are remappable. © 2007 Microchip Technology Inc. ...
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... PIC24HJ12GP201/202 Pin Diagrams 18-Pin SDIP, SOIC PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 28-Pin SDIP, SOIC PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSC/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 ASDA1/RP5/CN27/RB5 DS70282B-page 4 MCLR AN6/RP15/CN11/RB15 3 16 AN7/RP14/CN12/RB14 DDCORE SCL1/RP9/CN21/RB9 SDA1/RP8/CN22/RB8 11 9 INT0/RP7/CN23/RB7 ...
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... Pin Diagrams (Continued) 28-Pin QFN PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 PIC24HJ12GP202 Preliminary AN8/RP13/CN13/RB13 AN9/RP12/CN14/RB12 TMS/RP11/CN15/RB11 TDI/RP10/CN16/RB10 V DDCORE V SS TDO/SDA1/RP9/CN21/RB9 DS70282B-page 5 ...
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... PIC24HJ12GP201/202 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU ............................................................................................................................................................................................ 11 3.0 Memory Organization ................................................................................................................................................................. 17 4.0 Flash Program Memory .............................................................................................................................................................. 37 5.0 Resets ....................................................................................................................................................................................... 43 6.0 Interrupt Controller ..................................................................................................................................................................... 49 7.0 Oscillator Configuration .............................................................................................................................................................. 77 8.0 Power-Saving Features .............................................................................................................................................................. 87 9.0 I/O Ports ..................................................................................................................................................................................... 89 10.0 Timer1 ...................................................................................................................................................................................... 109 11.0 Timer2/3 Feature...................................................................................................................................................................... 111 12.0 Input Capture............................................................................................................................................................................ 117 13.0 Output Compare ....................................................................................................................................................................... 119 14 ...
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... DEVICE OVERVIEW Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive refer- ence source. To complement the informa- tion in this data sheet, refer to the “PIC24H Family Reference Manual”. Please see the Microchip web site (www.micro- chip.com) for the latest PIC24H Family Reference Manual chapters ...
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... FIGURE 1-1: PIC24HJ12GP201/202 BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCH PCL PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks Power-up Timing ...
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... I ST Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode ...
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... Positive supply for analog modules. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input O = Output Preliminary P = Power I = Input © 2007 Microchip Technology Inc. ...
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... The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. 2.2 Special MCU Features The PIC24HJ12GP201/202 features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit A ...
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... PIC24HJ12GP201/202 FIGURE 2-1: PIC24HJ12GP201/202 CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Interrupt Controller 8 23 PCU 23 Program Counter Stack Control Logic 23 Address Latch Program Memory Address Bus Data Latch 24 Instruction Decode & Control Control Signals to Various Blocks DS70282B-page 12 ...
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... FIGURE 2-2: PIC24HJ12GP201/202 PROGRAMMER’S MODEL PC22 0 7 TBLPAG Data Table Page Address 7 0 PSVPAG — — — — — — SRH © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 D15 D0 W0/WREG W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM PC0 0 Program Space Visibility Page Address ...
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... PIC24HJ12GP201/202 2.3 CPU Control Registers REGISTER 2-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (1) (2) R/W-0 R/W-0 R/W-0 (2) IPL<2:0> bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘ ...
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... Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — ...
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... PIC24HJ12GP201/202 2.4 Arithmetic Logic Unit (ALU) The PIC24HJ12GP201/202 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register ...
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... Manual to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG<7> to permit access to the features Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24HJ12GP201/202 device is shown in Figure 3-1. PIC24HJ12GP201/202 0x000000 GOTO Instruction 0x000002 Reset Address ...
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... A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJ12GP201/202 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs) ...
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... Data Address Space The PIC24HJ12GP201/202 CPU has a separate 16- bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space ...
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... PIC24HJ12GP201/202 FIGURE 3-3: DATA MEMORY MAP FOR PIC24HJ12GP201/202 DEVICES WITH 1 KB RAM MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 1 Kbyte SRAM Space 0x0BFF 0x0C01 0x1FFF 0x2001 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70282B-page 20 LSB 16 bits Address MSb LSb 0x0000 ...
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TABLE 3-1: CPU CORE REGISTERS MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Addr WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 ...
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... CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CNPU2 006A CN30PUE CN29PUE — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-3: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP201 SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr ...
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TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP SFR SFR Bit 15 Bit 14 Bit 13 Bit 12 Name Addr — — — INTCON1 0080 NSTDIS INTCON2 0082 ALTIVT DISI — — IFS0 0084 — — AD1IF U1TXIF IFS1 0086 — — ...
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TABLE 3-5: TIMER REGISTER MAP SFR Name SFR Bit 15 Bit 14 Bit 13 Bit 12 Addr TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON ...
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TABLE 3-8: I2C1 REGISTER MAP SFR SFR Name Bit 15 Bit 14 Bit 13 Bit 12 Addr I2C1RCV 0200 — — — — I2C1TRN 0202 — — — — I2C1BRG 0204 — — — — I2C1CON 0206 I2CEN — I2CSIDL ...
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... RPOR7 06CE — — — Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-13: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 RPOR0 06C0 — ...
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... TABLE 3-14: ADC1 REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD ...
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TABLE 3-15: ADC1 REGISTER MAP FOR PIC24HJ12GP202 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ...
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... LATB13 LATB12 ODCB 02CE ODCB15 ODCB14 ODCB13 ODCB12 Legend unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-18: PORTB REGISTER MAP FOR PIC24HJ12GP201 File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 TRISB 02C8 TRISB15 TRISB14 — ...
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TABLE 3-20: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 NVMCON 0760 WR WREN WRERR — NVMKEY 0766 — — — — Legend unknown value on Reset, — = unimplemented, read as ...
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... SOFTWARE STACK In addition to its use as a working register, the W15 register in the PIC24HJ12GP201/202 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4 ...
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... PIC24HJ12GP201/202 TABLE 3-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset (Register Indexed) Register Indirect with Literal Offset 3.3.3 MOVE (MOV) INSTRUCTION Move instructions provide a greater degree of addressing flexibility than other instructions ...
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... Interfacing Program and Data Memory Spaces The PIC24HJ12GP201/202 architecture uses a 24-bit- wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, mean- ing that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces ...
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... PIC24HJ12GP201/202 FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION (1) Program Counter (2) Table Operations (1) Program Space Visibility (Remapping) User/Configuration Space Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. ...
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... TBLPAG © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. ...
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... PIC24HJ12GP201/202 3.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored con- stant data from the data space without the need to use special instructions (such as TBLRDL/H) ...
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... Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a PIC24HJ12GP201/202 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming ...
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... PIC24HJ12GP201/202 4.2 RTSP Operation The PIC24HJ12GP201/202 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions time, and to program one row or one word at a time. The 8-row erase pages and single row ...
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... Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte Note 1: These bits can only be Reset on POR. 2: All other combinations of NVMOP<3:0> are unimplemented. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 U-0 — — (1) U-0 R/W-0 R/W-0 — ...
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... PIC24HJ12GP201/202 REGISTER 4-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 — — — bit 15 W-0 W-0 W-0 bit 7 Legend Satiable only bit R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY< ...
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... W1 MOV W1, NVMKEY BSET NVMCON, #WR NOP NOP © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 4. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). 5. Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming ...
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... PIC24HJ12GP201/202 EXAMPLE 4-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 MOV W0, NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 MOV W0, TBLPAG MOV #0x6000 Perform the TBLWT instructions to write the latches ...
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... RESETS Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST ...
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... PIC24HJ12GP201/202 REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-0 U-0 TRAPR IOPUWR — bit 15 R/W-0 R/W-0 R/W-0 EXTR SWR SWDTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TRAPR: Trap Reset Flag bit Trap Conflict Reset has occurred ...
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... WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) BOR (RCON<1>) POR (RCON<0>) Note 1: All Reset flag bits may be set or cleared by the user software. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 (1) (1) Setting Event Trap conflict event Illegal opcode or uninitialized W register access Configuration mismatch MCLR Reset ...
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... PIC24HJ12GP201/202 5.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 7.0 “Oscillator Configuration” for further details. ...
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... FRC oscillator and the user application can switch to the desired crystal oscillator in the Trap Service Routine. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 5.2.2.1 FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal ...
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... PIC24HJ12GP201/202 NOTES: DS70282B-page 48 Preliminary © 2007 Microchip Technology Inc. ...
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... Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24HJ12GP201/202 device clears its registers in response to a Reset, which forces the PC to zero. The digital signal controller then begins program execution at location 0x000000. The user application ...
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... PIC24HJ12GP201/202 FIGURE 6-1: PIC24HJ12GP201/202 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 Interrupt Vector 52 ...
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... Microchip Technology Inc. PIC24HJ12GP201/202 AIVT Address Interrupt Source 0x000114 INT0 – External Interrupt 0 0x000116 IC1 – Input Compare 1 0x000118 OC1 – Output Compare 1 0x00011A T1 – Timer1 0x00011C Reserved 0x00011E IC2 – Input Capture 2 0x000120 OC2 – ...
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... PIC24HJ12GP201/202 TABLE 6-1: INTERRUPT VECTORS (CONTINUED) Interrupt Vector Request (IRQ) IVT Address Number Number 54 46 0x000070 55 47 0x000072 56 48 0x000074 57 49 0x000076 58 50 0x000078 59 51 0x00007A 60 52 0x00007C 61 53 0x00007E 62 54 0x000080 63 55 0x000082 64 56 0x000084 65 57 0x000086 66 58 0x000088 67 59 ...
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... Interrupt Control and Status Registers PIC24HJ12GP201/202 devices implement a total of 17 registers for the interrupt controller: • Interrupt Control Register 1 (INTCON1) • Interrupt Control Register 2 (INTCON2) • Interrupt Flag Status Registers (IFSx) • Interrupt Enable Control Registers (IECx) • Interrupt Priority Control Registers (IPCx) • ...
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... PIC24HJ12GP201/202 REGISTER 6-1: SR: CPU STATUS REGISTER U-0 U-0 U-0 — — — bit 15 (3) (3) R/W-0 R/W-0 R/W-0 (2) (2) IPL2 IPL1 IPL0 bit 7 Legend Clear only bit R = Readable bit S = Set only bit W = Writable bit ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 IPL< ...
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... CPU interrupt priority level less Note 1: For complete register details, see Register 2-2: “CORCON: CORE Control Register”. 2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 (1) U-0 U-0 U-0 — ...
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... PIC24HJ12GP201/202 REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 NSTDIS — — bit 15 U-0 R/W-0 U-0 — DIV0ERR — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled ...
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... INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 ...
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... PIC24HJ12GP201/202 REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 — — AD1IF bit 15 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit ...
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... IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 59 ...
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... PIC24HJ12GP201/202 REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 — — INT2IF bit 15 R/W-0 R/W-0 U-0 IC8IF IC7IF — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt 2 Flag Status bit ...
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... Unimplemented: Read as ‘0’ bit 1 U1EIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... PIC24HJ12GP201/202 REGISTER 6-8: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — AD1IE bit 15 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 AD1IE: ADC1 Conversion Complete Interrupt Enable bit ...
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... IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 63 ...
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... PIC24HJ12GP201/202 REGISTER 6-9: IEC1: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 — — INT2IE bit 15 R/W-0 R/W-0 U-0 IC8IE IC7IE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interrupt 2 Enable bit ...
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... Bit is set bit 15-2 Unimplemented: Read as ‘0’ bit 1 U1EIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — U-0 U-0 U-0 — ...
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... PIC24HJ12GP201/202 REGISTER 6-11: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 — T1IP<2:0> bit 15 U-0 R/W-1 R/W-0 — IC1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — R/W-0 U-0 U-0 — — ...
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... PIC24HJ12GP201/202 REGISTER 6-13: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 — U1RXIP<2:0> bit 15 U-0 R/W-1 R/W-0 — SPI1EIP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... Unimplemented: Read as ‘0’ bit 2-0 U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 U-0 R/W-1 — ...
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... PIC24HJ12GP201/202 REGISTER 6-15: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 — CNIP<2:0> bit 15 U-0 R/W-1 R/W-0 — MI2C1IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 U-0 R/W-1 — U-0 U-0 R/W-1 — — ...
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... PIC24HJ12GP201/202 REGISTER 6-17: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 U-0 U-0 — — — bit 15 U-0 R/W-1 R/W-0 — INT2IP<2:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 INT2IP<2:0>: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • ...
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... U1EIP<2:0>: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) • • • 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-0 U-0 U-0 — ...
Page 76
... PIC24HJ12GP201/202 REGISTER 6-19: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 — — — bit 15 U-0 R-0 R-0 — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • ...
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... RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 6.4.3 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR ...
Page 78
... PIC24HJ12GP201/202 NOTES: DS70282B-page 76 Preliminary © 2007 Microchip Technology Inc. ...
Page 79
... OSCILLATOR CONFIGURATION Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters. ...
Page 80
... The output of the oscillator (or the output of the PLL if a PLL mode has been selected) F generate the device instruction clock (F defines the operating speed of the device, and speeds MHz are supported by the PIC24HJ12GP201/ 202 architecture. Instruction execution speed or device operating frequency given by: ...
Page 81
... PLL” being the selected oscillator mode. • If PLLPRE<4:0> then This yields a VCO input of 10 MHz, which is within the acceptable range of 0.8-8 MHz. FIGURE 7-2: PIC24HJ12GP201/202 PLL BLOCK DIAGRAM Source (Crystal, External Clock PLLPRE or Internal RC) Divide by TABLE 7-1: ...
Page 82
... PIC24HJ12GP201/202 REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 — COSC<2:0> bit 15 R/W-0 R/W-0 R-0 CLKLOCK IOLOCK LOCK bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 Unimplemented: Read as ‘0’ ...
Page 83
... OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 1 LPOSCEN: Secondary (LP) Oscillator Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 81 ...
Page 84
... PIC24HJ12GP201/202 REGISTER 7-2: CLKDIV: CLOCK DIVISOR REGISTER R/W-0 R/W-0 R/W-0 ROI DOZE<2:0> bit 15 R/W-0 R/W-1 U-0 PLLPOST<1:0> — bit 7 Legend Value set from Configuration bits on POR R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ROI: Recover on Interrupt bit ...
Page 85
... PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier) 000000000 = 2 000000001 = 3 000000010 = 4 • • • 000110000 = 50 (default) • • • 111111111 = 513 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — — R/W-1 R/W-0 R/W-0 PLLDIV<7:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 86
... PIC24HJ12GP201/202 REGISTER 7-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER U-0 U-0 U-0 — — — bit 15 U-0 U-0 R/W-0 — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits 011111 = Center frequency + 11 ...
Page 87
... Applications are free to switch among any of the four clock sources (Primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, PIC24HJ12GP201/202 devices have a safeguard lock built into the switch process. Note: Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD< ...
Page 88
... PIC24HJ12GP201/202 NOTES: DS70282B-page 86 Preliminary © 2007 Microchip Technology Inc. ...
Page 89
... Clock Frequency and Clock Switching PIC24HJ12GP201/202 devices allow a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits (OSCCON< ...
Page 90
... PIC24HJ12GP201/202 8.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 “ ...
Page 91
... I/O PORTS Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters. ...
Page 92
... NOP. An example is shown in Example 9-1. 9.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24HJ12GP201/202 devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled ...
Page 93
... These modules include I A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In ...
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... PIC24HJ12GP201/202 FIGURE 9-2: REMAPPABLE MUX INPUT FOR U1RX RP0 RP1 RP2 RP 15 TABLE 9-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Input Name External Interrupt 1 External Interrupt 2 Timer 2 External Clock Timer 3 External Clock Input Capture 1 Input Capture 2 Input Capture 7 Input Capture 8 Output Compare Fault A ...
Page 95
... SCK1OUT SS1OUT OC1 OC2 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 value of the bit field corresponds to one of the periph- erals, and that peripheral’s output is mapped to the pin (see Table 9-2 and Figure 9-3). The list of peripherals for output mapping also includes a null value of ‘ ...
Page 96
... PIC24HJ12GP201/202 9.4.3.3 Mapping The control schema of peripheral select pins is not lim- ited to a small range of fixed peripheral configurations. There are no mutual or hardware-enforced lockouts between any of the peripheral mapping SFRs. Literally any combination of peripheral mappings across any or all of the RPn pins is possible. This includes both many-to-one and one-to-many mappings of peripheral inputs and outputs to pins ...
Page 97
... Example 9-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 EXAMPLE 9-2: //************************************* // Unlock Registers //************************************* asm volatile ( "mov #OSCCONL, w1 ...
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... PIC24HJ12GP201/202 9.5 Peripheral Pin Select Registers The PIC24HJ12GP201/202 devices implement 17 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (9) • Output Remappable Peripheral Registers (8) Note: Input and Output Register values can only be changed if OSCCON<IOLOCK> See Section 9.4.4.1 “Control Register Lock” for a specific command sequence. ...
Page 99
... INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 INT2R<4:0> ...
Page 100
... PIC24HJ12GP201/202 REGISTER 9-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 T3CKR< ...
Page 101
... IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 IC2R<4:0> R/W-1 R/W-1 R/W-1 IC1R<4:0> ...
Page 102
... PIC24HJ12GP201/202 REGISTER 9-5: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTERS 10 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 IC8R< ...
Page 103
... OCFAR<4:0>: Assign Output Capture A (OCFA) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 — — R/W-1 R/W-1 R/W-1 OCFAR<4:0> ...
Page 104
... PIC24HJ12GP201/202 REGISTER 9-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 U1CTSR< ...
Page 105
... SDI1R<4:0>: Assign SPI 1 Data Input (SDI1) to the corresponding RPn pin bits 11111 = Input tied to V 01111 = Input tied to RP15 • • • 00001 = Input tied to RP1 00000 = Input tied to RP0 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 R/W-1 R/W-1 SCK1R<4:0> R/W-1 R/W-1 R/W-1 SDI1R<4:0> ...
Page 106
... PIC24HJ12GP201/202 REGISTER 9-9: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-5 Unimplemented: Read as ‘0’ bit 4-0 SS1R< ...
Page 107
... Unimplemented: Read as ‘0’ bit 4-0 RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 9-2 for periph- eral function numbers) © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP1R<4:0> R/W-0 R/W-0 R/W-0 RP0R< ...
Page 108
... PIC24HJ12GP201/202 REGISTER 9-12: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTERS 2 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP5R< ...
Page 109
... RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 9-2 for peripheral function numbers) bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 9-2 for peripheral function numbers) © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 RP9R<4:0> R/W-0 R/W-0 R/W-0 RP8R< ...
Page 110
... PIC24HJ12GP201/202 REGISTER 9-16: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTERS 6 U-0 U-0 U-0 — — — bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12-8 RP13R< ...
Page 111
... TIMER1 Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters. The Timer1 module is a 16-bit timer, which can serve as the time counter for the real-time clock, or operate as a free-running interval timer/counter ...
Page 112
... PIC24HJ12GP201/202 REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as ‘ ...
Page 113
... TIMER2/3 FEATURE Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters. ...
Page 114
... PIC24HJ12GP201/202 FIGURE 11-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T3IF 0 (2) ADC Event Trigger Equal MSb Reset Read TMR2 Write TMR2 Data Bus<15:0> Note 1: The 32-bit timer control bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register ...
Page 115
... FIGURE 11-2: TIMER2 (16-BIT) BLOCK DIAGRAM T2CK TGATE 1 Set T2IF 0 Reset Equal © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 1x Gate Sync TMR2 Sync Comparator PR2 Preliminary TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 TCS TGATE DS70282B-page 113 ...
Page 116
... PIC24HJ12GP201/202 REGISTER 11-1: T2CON CONTROL REGISTER R/W-0 U-0 R/W-0 TON — TSIDL bit 15 U-0 R/W-0 R/W-0 — TGATE bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 TON: Timer2 On bit When T32 = Starts 32-bit Timer2 Stops 32-bit Timer2/3 ...
Page 117
... External clock from pin T3CK (on the rising edge Internal clock (F CY bit 0 Unimplemented: Read as ‘0’ Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all timer functions are set through T2CON. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 (1) — — R/W-0 U-0 (1) — ...
Page 118
... PIC24HJ12GP201/202 NOTES: DS70282B-page 116 Preliminary © 2007 Microchip Technology Inc. ...
Page 119
... Reference chapters. The input capture module is useful in applications requiring frequency (period) and pulse measurement. The PIC24HJ12GP201/202 devices support up to eight input capture channels. The input capture module captures the 16-bit value of the selected Time Base register when an event occurs at the ICx pin. The events that cause a capture event are listed below in three categories: • ...
Page 120
... PIC24HJ12GP201/202 12.1 Input Capture Registers REGISTER 12-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER U-0 U-0 R/W-0 — — ICSIDL bit 15 R/W-0 R/W-0 R/W-0 ICTMR ICI<1:0> bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-14 Unimplemented: Read as ‘0’ ...
Page 121
... OUTPUT COMPARE Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive refer- ence source. To complement the informa- tion in this data sheet, refer to the “PIC24H Family Reference Manual”. Please see the Microchip web site (www.micro- chip.com) for the latest PIC24H Family Reference Manual chapters ...
Page 122
... PIC24HJ12GP201/202 13.3 Pulse-Width Modulation (PWM) Mode Use the following steps when configuring the output compare module for PWM operation: 1. Set the PWM period by writing to the selected Timer Period register (PRy). 2. Set the PWM duty cycle by writing to the OCxRS register. 3. Write the OxCR register with the initial duty cycle. ...
Page 123
... FFFFh Resolution (bits) 16 TABLE 13-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MIPS (F PWM Frequency 76 Hz Timer Prescaler Ratio 8 Period Register Value FFFFh Resolution (bits) 16 © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 • (Timer2 Prescale Value) /F )/log 2) bits PWM 10 2) bits 122 Hz 977 ...
Page 124
... PIC24HJ12GP201/202 FIGURE 13-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM (1) OCxRS (1) OCxR Comparator OCTSEL TMR register inputs (3) from time bases Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels 1 through 8. 2: OCFA pin controls OC1-OC2 channels. ...
Page 125
... Compare event toggles OCx pin 010 = Initialize OCx pin high, compare event forces OCx pin low 001 = Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 126
... PIC24HJ12GP201/202 NOTES: DS70282B-page 124 Preliminary © 2007 Microchip Technology Inc. ...
Page 127
... SERIAL PERIPHERAL INTERFACE (SPI) Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters ...
Page 128
... PIC24HJ12GP201/202 FIGURE 14-1: SPI MODULE BLOCK DIAGRAM SCKx SSx Sync Control Clock Control SDOx bit 0 SDIx SPIxSR Transfer SPIxRXB SPIxBUF Read SPIxBUF DS70282B-page 126 1:1 to 1:8 Secondary Prescaler Select Edge Shift Control Transfer SPIxTXB Write SPIxBUF 16 Internal Data Bus Preliminary 1:1/4/16/64 ...
Page 129
... User application must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. FIGURE 14-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PIC24H FIGURE 14-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PIC24H © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 PROCESSOR 2 (SPI Slave) SDOx SDIx Serial Receive Buffer SDIx SDOx LSb MSb ...
Page 130
... PIC24HJ12GP201/202 FIGURE 14-5: SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PIC24H FIGURE 14-6: SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PIC24H EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED F SCK TABLE 14-1: SAMPLE SCKx FREQUENCIES MHz CY Primary Prescaler Settings MHz CY Primary Prescaler Settings Note: SCKx frequencies shown in kHz ...
Page 131
... SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — — ...
Page 132
... PIC24HJ12GP201/202 REGISTER 14-2: SPI CON1: SPIx CONTROL REGISTER 1 X U-0 U-0 U-0 — — — bit 15 R/W-0 R/W-0 R/W-0 SSEN CKP MSTEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 Unimplemented: Read as ‘0’ bit 12 ...
Page 133
... PPRE<1:0>: Primary Prescale bits (Master mode Primary prescale 1 Primary prescale 4 Primary prescale 16 Primary prescale 64:1 Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 131 ...
Page 134
... PIC24HJ12GP201/202 REGISTER 14-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 FRMEN SPIFSD FRMPOL bit 15 U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (SSx pin used as frame sync pulse input/output) ...
Page 135
... INTER-INTEGRATED CIRCUIT Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters. ...
Page 136
... PIC24HJ12GP201/202 2 FIGURE 15-1: I C™ BLOCK DIAGRAM ( Shift SCLx Clock SDAx Shift Clock BRG Down Counter DS70282B-page 134 = 1) X I2CxRCV I2CxRSR LSb Address Match Match Detect I2CxADD Start and Stop Bit Detect Start and Stop Bit Generation Collision Detect Acknowledge Generation ...
Page 137
... Intelligent Peripheral Management Interface (IPMI). When this bit is set, the module accepts and acts upon all addresses. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 15.8 General Call Address Support The general call address can address all devices. When this address is used, all devices should, in theory, respond with an Acknowledgement ...
Page 138
... PIC24HJ12GP201/202 15.11 Slope Control 2 The I C standard requires slope control on the SDAx and SCLx signals for Fast mode (400 kHz). The control bit, DISSLW, enables the user application to disable slew rate control if desired necessary to disable the slew rate control for 1 MHz mode. ...
Page 139
... General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I Used in conjunction with SCLREL bit Enable software or receive clock stretching 0 = Disable software or receive clock stretching © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-1 HC R/W-0 R/W-0 SCLREL IPMIEN A10M ...
Page 140
... PIC24HJ12GP201/202 REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I Value that will be transmitted when the software initiates an Acknowledge sequence Send NACK during Acknowledge 0 = Send ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit 2 (when operating Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit ...
Page 141
... Hardware clear at device address match. Hardware set by reception of slave byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 R/C-0 HS — — R/C-0 HSC ...
Page 142
... PIC24HJ12GP201/202 REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating Read – ...
Page 143
... AMSKx: Mask for Address bit x Select bit 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 U-0 U-0 U-0 — ...
Page 144
... PIC24HJ12GP201/202 NOTES: DS70282B-page 142 Preliminary © 2007 Microchip Technology Inc. ...
Page 145
... UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H ...
Page 146
... PIC24HJ12GP201/202 16.1 UART Baud Rate Generator The UART module includes a dedicated 16-bit BRG. The BRGx register controls the period of a free-running 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 16-1: UART BAUD RATE WITH ...
Page 147
... Write 0x55 to UxTXREG, which loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 16.5 Receiving in 8-bit or 9-bit Data Mode 1. Set up the UART (as described in Section 16.2 “ ...
Page 148
... PIC24HJ12GP201/202 REGISTER 16-1: UxMODE: UART R/W-0 U-0 R/W-0 UARTEN — USIDL bit 15 R/W-0 HC R/W-0 R/W-0 HC WAKE LPBACK ABAUD bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 UARTEN: UARTx Enable bit 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0> ...
Page 149
... STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: This feature is only available for the 16x BRG mode (BRGH = 0). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 MODE REGISTER (CONTINUED) x Preliminary DS70282B-page 147 ...
Page 150
... PIC24HJ12GP201/202 REGISTER 16-2: U STA: UART x R/W-0 R/W-0 R/W-0 (1) UTXISEL1 UTXINV UTXISEL0 bit 15 R/W-0 R/W-0 R/W-0 URXISEL<1:0> ADDEN bit 7 Legend Hardware cleared R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use ...
Page 151
... Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 STATUS AND CONTROL REGISTER (CONTINUED) x Preliminary DS70282B-page 149 ...
Page 152
... PIC24HJ12GP201/202 NOTES: DS70282B-page 150 Preliminary © 2007 Microchip Technology Inc. ...
Page 153
... Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters. The PIC24HJ12GP201/202 devices have ADC module input channels. The AD12B bit (AD1CON1<10>),allows each of the ADC modules to be configured as either a 10-bit, 4- sample-and-hold ADC (default configuration 12- bit, 1-sample-and-hold ADC. Note: The ADC module must be disabled before the AD12B bit can be modified ...
Page 154
... PIC24HJ12GP201/202 FIGURE 17-1: ADC1 MODULE BLOCK DIAGRAM ( REF ( REF AN0 AN0 AN3 AN6 AN9 V REF AN1 AN1 AN4 AN7 V REF AN2 AN2 AN5 AN8 V REF 00000 00001 00010 00011 AN3 00100 AN4 00101 AN5 00110 AN6 00111 AN7 01000 AN8 01001 ...
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... ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADC Internal RC Clock T CY OSC ( Note: Refer to Figure 7-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, F the clock source frequency. T © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 = T (ADCS + – 1 ADCS = – V 512 * (V – ...
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... PIC24HJ12GP201/202 REGISTER 17-1: AD1CON1: ADC1 CONTROL REGISTER 1 (where R/W-0 U-0 R/W-0 ADON — ADSIDL bit 15 R/W-0 R/W-0 R/W-0 SSRC<2:0> bit 7 Legend Cleared by hardware R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating ...
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... Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear DONE status (software not allowed to write ‘1’). Clearing this bit will NOT affect any operation in progress. Automatically cleared by hardware at start of a new conversion. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Preliminary DS70282B-page 155 ...
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... PIC24HJ12GP201/202 REGISTER 17-2: AD1CON2: ADC1 CONTROL REGISTER 2 (where R/W-0 R/W-0 R/W-0 VCFG<2:0> bit 15 R-0 U-0 R/W-0 BUFS — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-13 VCFG<2:0>: Converter Voltage Reference Configuration bits ADREF+ A 000 VDD ...
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... T CY • • • 000010 = T · (ADCS<7:0> · 000001 = T · (ADCS<7:0> · 000000 = T · (ADCS<7:0> · © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 R/W-0 R/W-0 R/W-0 SAMC<4:0> R/W-0 R/W-0 R/W-0 ADCS<5:0> Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared = ...
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... Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 15-11 Unimplemented: Read as ‘0’ bit 10-9 CH123NB<1:0>: Channel Negative Input Select for Sample B bits PIC24HJ12GP201 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input is V ...
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... REGISTER 17-4: AD1CHS123: ADC1 INPUT CHANNEL SELECT REGISTER (CONTINUED) bit 2-1 CH123NA<1:0>: Channel Negative Input Select for Sample A bits PIC24HJ12GP201 devices only: If AD12B = Reserved 10 = Reserved 01 = Reserved 00 = Reserved If AD12B = Reserved 10 = Reserved 01 = CH1, CH2, CH3 negative input CH1, CH2, CH3 negative input is V PIC24HJ12GP202 devices only: ...
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... Channel 0 negative input is AN1 0 = Channel 0 negative input is V bit 6-5 Unimplemented: Read as ‘0’ bit 4-0 CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits PIC24HJ12GP201 devices only: 00101 = Channel 0 positive input is AN5 • • • 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 ...
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... Skip ANx for input scan Note 1: On devices without nine analog inputs, all AD1CSSL bits can be selected. However, inputs selected for scan without a corresponding input on device will convert ADREF-. 2: PIC24HJ12GP201 devices support only 6 channels (CSS0-CSS5). REGISTER 17-7: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW U-0 U-0 U-0 — ...
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... PIC24HJ12GP201/202 NOTES: DS70282B-page 162 Preliminary © 2007 Microchip Technology Inc. ...
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... SPECIAL FEATURES Note: This data sheet summarizes the features of the PIC24HJ12GP201/202 devices not intended comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Please see the Microchip web site (www.microchip.com) for PIC24H Family Reference chapters. ...
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... PIC24HJ12GP201/202 TABLE 18-2: PIC24HJ12GP201/202 CONFIGURATION BITS DESCRIPTION Bit Field Register BWRP FBS BSS<2:0> FBS GSS<1:0> FGS GWRP FGS IESO FOSCSEL FNOSC<2:0> FOSCSEL FCKSM<1:0> FOSC IOL1WAY FOSC OSCIOFNC FOSC POSCMD<1:0> FOSC DS70282B-page 164 Description Boot Segment Program Flash Write Protection 1 = Boot segment may be written ...
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... TABLE 18-2: PIC24HJ12GP201/202 CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register FWDTEN FWDT WINDIS FWDT WDTPRE FWDT WDTPOST<3:0> FWDT ALTI2C FPOR FPWRT<2:0> FPOR © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. ...
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... This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24HJ12GP201/202 family incorporate an on-chip regulator that allows the device to run its core logic from V ...
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... Watchdog Timer (WDT) For PIC24HJ12GP201/202 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 18.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation ...
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... PIC24HJ12GP201/202 18.5 JTAG Interface PIC24HJ12GP201/202 devices implement a JTAG interface, which supports boundary scan device test- ing, as well as in-circuit programming. Detailed infor- mation on this interface will be provided in future revisions of the document. 18.6 Code Protection and CodeGuard™ Security The PIC24HJ12GP201/202 devices intermediate implementation of CodeGuard Security. ...
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... In-Circuit Serial Programming PIC24HJ12GP201/202 family digital signal controllers can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers ...
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... PIC24HJ12GP201/202 NOTES: DS70282B-page 170 Preliminary © 2007 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY Note: This data sheet summarizes the features of this group of PIC24HJ12GP201/202 devices not intended comprehensive reference source. complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest PIC24H Family Reference Manual chapters ...
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... PIC24HJ12GP201/202 All instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. ...
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... One of 16 source working registers ∈ {W0..W15} Wns WREG W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws Source W register ∈ Wso { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Preliminary DS70282B-page 173 ...
Page 176
... PIC24HJ12GP201/202 TABLE 19-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # ADD f 1 ADD ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG AND #lit10,Wn AND Wb,Ws,Wd ...
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... FF1R FF1R Ws,Wnd 34 GOTO GOTO Expr GOTO Wn © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Bit Test f Bit Test Bit Test Bit Test Ws<Wb> Bit Test Ws<Wb> Bit Test then Set f Bit Test then Set Bit Test then Set Call subroutine Call indirect subroutine ...
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... PIC24HJ12GP201/202 TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 35 INC INC f INC f,WREG INC Ws,Wd 36 INC2 INC2 f INC2 f,WREG INC2 Ws,Wd 37 IOR IOR f IOR f,WREG IOR #lit10,Wn IOR Wb,Ws,Wd IOR Wb,#lit5,Wd 38 LNK LNK #lit14 39 LSR LSR f LSR ...
Page 179
... SWAP SWAP.b Wn SWAP Wn 65 TBLRDH TBLRDH Ws,Wd © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Description Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn times Software device Reset Return from interrupt Return with literal in Wn Return from Subroutine f = Rotate Left through Carry f ...
Page 180
... PIC24HJ12GP201/202 TABLE 19-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 66 TBLRDL TBLRDL Ws,Wd 67 TBLWTH TBLWTH Ws,Wd 68 TBLWTL TBLWTL Ws,Wd 69 ULNK ULNK 70 XOR XOR f XOR f,WREG XOR #lit10,Wn XOR Wb,Ws,Wd XOR Wb,#lit5, Ws,Wnd DS70282B-page 178 Description Read Prog<15:0> Write Ws<7:0> to Prog<23:16> ...
Page 181
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 20.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 182
... PIC24HJ12GP201/202 20.2 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 183
... Microchip Technology Inc. PIC24HJ12GP201/202 20.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, ...
Page 184
... PIC24HJ12GP201/202 20.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 185
... This section provides an overview of PIC24HJ12GP201/202 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24HJ12GP201/202 family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied ...
Page 186
... Symbol DMAX Symbol θ JA θ JA θ JA θ JA θ JA θ numbers are achieved by package simulations Preliminary Max MIPS PIC24HJ12GP201/202 40 35 Min Typ Max Unit -40 — +125 °C -40 — +85 °C -40 — +140 °C -40 — +125 ° INT – T )/θ ...
Page 187
... Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. 2: This is the limit to which These parameters are characterized but not tested in manufacturing. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature (1) Min Typ Max 3.0 — ...
Page 188
... PIC24HJ12GP201/202 TABLE 21-5: DC CHARACTERISTICS: OPERATING CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC20d 24 30 DC20a 27 30 DC20b 27 30 DC20c 27 35 DC21d 30 40 DC21a 31 40 DC21b 32 45 DC21c 33 45 DC22d 35 50 DC22a 38 50 DC22b 38 55 DC22c 39 55 DC23d 47 70 DC23a ...
Page 189
... Peripheral Module IDLE Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to V © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 ) IDLE Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40° ...
Page 190
... PIC24HJ12GP201/202 TABLE 21-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Power-Down Current ( DC60d 290 500 DC60a 293 500 DC60b 317 500 DC60c 245 1 DC61d 8 13 DC61a 10 15 DC61b 12 20 DC61c 13 25 Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. ...
Page 191
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T ...
Page 192
... PIC24HJ12GP201/202 TABLE 21-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Output Low Voltage OL DO10 I/O ports DO16 OSC2/CLKO V Output High Voltage OH DO20 I/O ports DO26 OSC2/CLKO TABLE 21-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param Symbol Characteristic No. BO10 V BOR Event on V ...
Page 193
... A Param Symbol Characteristics No. C External Filter Capacitor EFC Value © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ +85°C for Industrial Operating temperature A -40°C ≤ T ≤ +125°C for Extended A (1) ...
Page 194
... PIC24HJ12GP201/202 21.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC24HJ12GP201/202 AC characteristics and timing parameters. TABLE 21-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – CHARACTERISTICS FIGURE 21-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 – for all pins except OSC2 ...
Page 195
... OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. 3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 ...
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... PIC24HJ12GP201/202 TABLE 21-17: PLL CLOCK TIMING SPECIFICATIONS (V AC CHARACTERISTICS Param Symbol Characteristic No. OS50 F PLL Voltage Controlled PLLI Oscillator (VCO) Input Frequency Range OS51 F On-Chip VCO System SYS Frequency OS52 T PLL Start-up Time (Lock Time) LOCK OS53 D CLKO Stability (Jitter) CLK Note 1: Data in “ ...
Page 197
... INP DI40 T CNx High or Low Time (input) RBP Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 DI35 DI40 New Value DO31 DO32 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T ≤ ...
Page 198
... PIC24HJ12GP201/202 FIGURE 21-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS V SY12 DD MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal Reset Watchdog Timer Reset I/O Pins SY35 FSCM Delay Note: Refer to Figure 21-1 for load conditions. ...
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... FSCM Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) -40°C ≤ T Operating temperature -40°C ≤ T (1) ...
Page 200
... PIC24HJ12GP201/202 FIGURE 21-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRx Note: Refer to Figure 21-1 for load conditions. TABLE 21-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TA10 T H TxCK High Time TX TA11 T L TxCK Low Time TX TA15 T P TxCK Input Period Synchronous, ...