PIC24FJ48GA002-I/SS Microchip Technology, PIC24FJ48GA002-I/SS Datasheet - Page 5

• Manufacturer Part Number: PIC24FJ48GA002-I/SS
• Description: IC PIC MCU FLASH 48K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ48GA002-I/SS

• Core Size: 16-Bit
• Program Memory Size: 48KB (16K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5. Module: Core
6. Module: Core
7. Module: A/D
 2010 Microchip Technology Inc.
On a Brown-out Reset, both the BOR and POR
bits may be set. This may cause the Brown-out
Reset condition to be indistinguishable from the
Power-on Reset.
Work around
None.
Affected Silicon Revisions
The PIC24FJ16GA002 and PIC24FJ16GA004
devices have 8K of data RAM implemented
instead of 4K. This will cause the address error
trap not to function for addresses between 2000h
and 27FFh.
Work around
Do not access RAM beyond address 17FFh to
maintain software compatibility with future device
revisions.
Affected Silicon Revisions
The AD1PCFG and AD1CHS registers allow
unimplemented channels to be selected. If these
channels are selected, they will read as if tied to
V
Work around
Disable channels, AN13 and AN14, in the
AD1PCFG register by ensuring that bits 13 and 14
are cleared.
Ensure that bits 5 and 12 of AD1CHS are main-
tained cleared. If these bits are set, it will cause the
ADC to reference channels AN16-31.
Affected Silicon Revisions
A3/
A3/
A3/
SS
A4
A4
A4
X
X
X
. These channels should be disabled.
B4
B4
B4
B5
B5
B5
B8
B8
B8
PIC24FJ64GA004 FAMILY
8. Module: A/D
9. Module: A/D
The A/D module will not generate code 511. Any
conversion which should result in 511 normally, will
instead generate 510 or 512.
Work around
None.
Affected Silicon Revisions
With the External Interrupt 0 (INT0) selected to start
an A/D conversion (SSRC<2:0> = 001), the device
may not wake-up from Sleep or Idle mode if more
than one conversion is selected per interrupt
(SMPI<3:0> <> 0000). Interrupts are generated
correctly if the device is not in a Sleep or Idle mode.
Work around
Configure the A/D to generate an interrupt after
every
another wake-up source, such as the WDT or
another interrupt source, to exit the Sleep or Idle
mode. Alternatively, perform A/D conversions in
Run mode.
Affected Silicon Revisions
A3/
A3/
A4
A4
X
X
B4
B4
conversion
B5
B5
B8
B8
(SMPI<3:0> = 0000).
DS80470E-page 5
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