PIC24FJ48GA002-I/SS Microchip Technology, PIC24FJ48GA002-I/SS Datasheet - Page 8

• Manufacturer Part Number: PIC24FJ48GA002-I/SS
• Description: IC PIC MCU FLASH 48K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ48GA002-I/SS

• Core Size: 16-Bit
• Program Memory Size: 48KB (16K x 24)
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-SSOP
• Controller Family/series: PIC24
• No. Of I/o's: 21
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• No. Of Pwm Channels: 5
• Embedded Interface Type: I2C, SPI, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164338 - MOD SKT PIC24F/DSPIC33F 28SOICDV164033 - KIT START EXPLORER 16 MPLAB ICD2
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ64GA004 FAMILY
19. Module: SPI
DS80470E-page 8
In SPI Slave mode (MSTEN = 0), with the slave
select option enabled (SSEN = 1), the peripheral
may accept transfers regardless of the SSx pin
state. The received data in SPIxBUF will be
accurate but not intended for the device.
Work around
There is a work around using the Peripheral Pin
Select (PPS) feature. One of the external inter-
rupts (INT1 or INT2) can be mapped to the same
pin as the SSx signal or the SSx signal can be
mapped to a pin with interrupt-on-change (CNx)
functionality. If the SSx signal changes to low
(active), the interrupt flag will be set.
When an SPI data received interrupt occurs, the
interrupt flag can be tested. If the interrupt mapped
to SSx did not occur, discard the data.
Affected Silicon Revisions
A3/
A4
X
B4
B5
B8
20. Module: SPI
When using Enhanced Buffer mode, an interrupt
will not occur if the following conditions exist:
• SPI Buffer Interrupt mode, SISEL<2:0>
• Slave Select mode is enabled (SSEN = 1).
This only occurs when Enhanced mode, Slave
Select mode and interrupt on Shift register empty
are all enabled. In other modes, the interrupt will
work correctly.
Work around
When Slave Select mode is enabled, interrupting
on SPIxSR empty and TX empty will occur at the
same time. Therefore, interrupting on TX FIFO
empty (SISEL<2:0> = 110) can be used as an
alternative to interrupting when the Shift register is
empty (SISEL<2:0> = 101).
Affected Silicon Revisions
A3/
A4
(SPIxSTAT<4:2>), is set to interrupt when the
Shift register is empty (SISEL<2:0> = 101).
X
B4
B5
 2010 Microchip Technology Inc.
B8