PIC18F26J50-I/SO Microchip Technology, PIC18F26J50-I/SO Datasheet - Page 135

• Manufacturer Part Number: PIC18F26J50-I/SO
• Description: IC PIC MCU FLASH 64K 2V 28-SOIC
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26J50-I/SO

• Program Memory Type: FLASH
• Program Memory Size: 64KB (32K x 16)
• Package / Case: 28-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 16
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 2.15 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3776 B
• Interface Type: EUSART, I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM183032, DV164136, MA180024, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 10 Channel
• Package: 28SOIC W
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 48 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 10-9:
TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
© 2008 Microchip Technology Inc.
PORTE
LATE
TRISE
SLRCON
ANSEL
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE.
Note 1:
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
MCLR/V
RE3
Legend:
Note 1:
Name
(1,2)
(2)
2:
3:
2:
(3)
Pin
PP
/
Implemented only when Master Clear functionality is disabled (MCLRE Configuration bit = 0).
RE3 is the only PORTE bit implemented on both PIC18F2XK20 and PIC18F4XK20 devices. All other bits
are implemented only when PORTE is implemented (i.e., PIC18F4XK20 devices).
Unimplemented on PIC18F2XK20 devices.
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
RE3 is available on both PIC18F2XK20 and PIC18F4XK20 devices. All other PORTE pins are only implemented on
PIC18F4XK20 devices.
RE3 does not have a corresponding TRIS bit to control data direction.
ANS7
Bit 7
IBF
—
—
—
PORTE I/O SUMMARY
Function
(3)
MCLR
RE0
AN5
RE1
AN6
RE2
AN7
RE3
WR
V
RD
CS
PP
ANS6
Bit 6
OBF
—
—
—
Setting
TRIS
—
(3)
—
—
0
1
1
1
0
1
1
1
0
1
1
1
(2)
ANS5
IBOV
Bit 5
I/O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
—
—
—
(3)
Type
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
I/O
ST
ST
ST
ST
ST
PSPMODE
SLRE
Preliminary
ANS4
Bit 4
—
—
LATE<0> data output; not affected by analog input.
PORTE<0> data input; disabled when analog input enabled.
PSP read enable input (PSP enabled).
A/D input channel 5; default input configuration on POR.
LATE<1> data output; not affected by analog input.
PORTE<1> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 6; default input configuration on POR.
LATE<2> data output; not affected by analog input.
PORTE<2> data input; disabled when analog input enabled.
PSP write enable input (PSP enabled).
A/D input channel 7; default input configuration on POR.
External Master Clear input; enabled when MCLRE Configuration bit is
set.
High-voltage detection; used for ICSP™ mode entry detection. Always
available, regardless of pin mode.
PORTE<3> data input; enabled when MCLRE Configuration bit is
clear.
(3)
SLRD
RE3
ANS3
PIC18F2XK20/4XK20
Bit 3
—
—
(1,2)
(3)
LATE Data Output Register
TRISE2
SLRC
ANS2
Bit 2
RE2
Description
TRISE1
SLRB
ANS1
Bit 1
RE1
TRISE0
SLRA
ANS0
Bit 0
DS41303D-page 133
RE0
on page
Values
Reset
60
60
60
61
60