DSPIC30F2011-20I/P Microchip Technology, DSPIC30F2011-20I/P Datasheet - Page 134

• Manufacturer Part Number: DSPIC30F2011-20I/P
• Description: IC DSPIC MCU/DSP 12K 18DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2011-20I/P

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 20 MIPS
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 12
• Flash Memory Size: 12KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 18PDIP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 12
• Interface Type: I2C/SPI/UART
• On-chip Adc: 8-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC30F005 - MODULE SCKT DSPIC30F 18DIP/SOICACICE0202 - ADAPTER MPLABICE 18P 300 MIL
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F2011-20IP

TABLE 17-7:
TABLE 17-8:
RCON
OSCCON
OSCTUN
PMD1
PMD2
Legend:
Note
FOSC
FWDT
FBORPOR
FGS
FICD
Legend:
Note
SFR Name Addr.
File Name
1:
2:
3:
1:
2:
3:
— = unimplemented bit, read as ‘0’
Reset state depends on type of Reset.
Reset state depends on Configuration bits.
Only available on dsPIC30F3013.
— = unimplemented bit, read as ‘0’
These bits are always read as ‘1’.
The FGS<2> bit is a read-only copy of the GCP bit (FGS<1>).
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
0740
0742
0744
0770
0772
F80000
F80002
F80004
F8000A
F8000C
Addr.
TRAPR
SYSTEM INTEGRATION REGISTER MAP
DEVICE CONFIGURATION REGISTER MAP
Bit 15
—
—
—
—
Bits 23-16
—
—
—
—
—
IOPUWR
Bit 14
—
—
—
COSC<2:0>
FWDTEN
MCLREN
Bit 15
FCKSM<1:0>
Bit 13
BGST LVDEN
T3MD
—
—
—
—
Bit 12
T2MD
Bit 14
—
—
—
—
—
—
Bit 11
T1MD
Bit 13
—
—
—
—
—
—
—
—
Bit 10
Bit 12
—
—
—
LVDL<3:0>
—
—
—
—
—
NOSC<2:0>
IC2MD IC1MD
Bit 9
Bit 11
—
—
—
—
—
—
—
Bit 8
Reserved
—
—
Bit 10
—
—
—
I2CMD U2MD
EXTR
Bit 7
—
—
(1)
POST<1:0>
Reserved
FOS<2:0>
SWR
Bit 6
Bit 9
—
—
—
—
—
(3)
(1)
SWDTEN
U1MD
LOCK
Bit 5
Reserved
—
—
Bit 8
—
—
—
WDTO
(1)
Bit 4
—
—
—
—
BOREN
BKBUG
Bit 7
—
—
—
SPI1MD
SLEEP
TUN3
Bit 3
CF
—
Bit 6
COE
—
—
—
—
TUN2
Bit 2
IDLE
—
—
—
Bit 5
FWPSA<1:0>
BORV<1:0>
—
—
—
LPOSCEN
OC2MD
TUN1
Bit 1
BOR
—
Bit 4
—
—
OSWEN
ADCMD
Bit 3
OC1MD
TUN0
—
—
—
Bit 0
POR
Reserved
FPR<4:0>
Bit 2
0000 0000 0000 0000
0000 0000 0000 0000
FWPSB<3:0>
—
—
(2)
Reset State
(Note 1)
(Note 2)
(Note 2)
Bit 1
GCP
FPWRT<1:0>
ICS<1:0>
GWRP
Bit 0