DSPIC30F2012-20I/SO Microchip Technology, DSPIC30F2012-20I/SO Datasheet
DSPIC30F2012-20I/SO
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... Microchip Technology Inc. Data Sheet High-Performance Digital Signal Controllers Preliminary DS70139C ...
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... PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... High current sink/source I/O pins: 25 mA/25 mA • Three 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules • 16-bit Capture input functions © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • 16-bit Compare/PWM output functions: • 3-wire SPI™ modules (supports four Frame ...
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... Sensor Family Program Memory Device Pins Bytes Instructions dsPIC30F2011 18 12K 4K dsPIC30F3012 18 24K 8K dsPIC30F2012 28 12K 4K dsPIC30F3013 28 24K 8K Pin Diagrams 18-Pin PDIP and SOIC EMUD3/AN0/V EMUD3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin SPDIP and SOIC ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F2011 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 15 Preliminary DS70139C-page 3 ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0. DS70139C-page AN8/OC1/RB8 2 20 AN9/OC2/RB9 3 19 CN17/RF4 dsPIC30F2012 4 18 CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 15 Preliminary © 2005 Microchip Technology Inc. ...
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... Pin Diagram 44-Pin QFN PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 Note: For descriptions of individual pins, see Section 1.0. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F3012 Preliminary 33 OSC2/CLKO/RC15 32 OSC1/CLKI AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 DS70139C-page 5 ...
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... Pin Diagrams 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 AN9/OC2/RB9 AN8/OC1/RB8 Note: For descriptions of individual pins, see Section 1.0. DS70139C-page dsPIC30F3013 Preliminary OSC2/CLKO/RC15 OSC1/CLKI AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 © 2005 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 7 ...
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... NOTES: DS70139C-page 8 Preliminary © 2005 Microchip Technology Inc. ...
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... The following block diagrams depict the architecture for these devices: • Figure 1-1 illustrates the dsPIC30F2011 • Figure 1-2 illustrates the dsPIC30F2012 • Figure 1-3 illustrates the dsPIC30F3012 • Figure 1-4 illustrates the dsPIC30F3013 Following the block diagrams, Table 1-1 relates the I/O functions to pinout information ...
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... PORTC 16 16 DSP Divide Engine Unit ALU<16> PORTD Input Output 2 Capture Compare I C™ Module Module Timers SPI1 UART1 Preliminary EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 © 2005 Microchip Technology Inc. ...
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... FIGURE 1-2: dsPIC30F2012 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Address Latch Control Logic Program Memory (12 Kbytes) Data Latch 16 ROM Latch 24 16 Instruction Decode & Control Power-up Timer ...
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... PORTC 16 16 DSP Divide Engine Unit ALU<16> PORTD Input Output 2 I C™ Capture Compare Module Module Timers SPI1 UART1 Preliminary EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 © 2005 Microchip Technology Inc. ...
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... Timing Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low Voltage Detect 12-bit ADC Capture Module © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM (1 Kbytes) (1 Kbytes) 16 Address Address Latch Latch 16 16 ...
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... PORTC is a bidirectional I/O port. ST PORTD is a bidirectional I/O port. ST PORTF is a bidirectional I/O port. ST Synchronous serial clock input/output for SPI1. ST SPI1 Data In. — SPI1 Data Out. ST SPI1 Slave Synchronization. Analog input Output = Power Preliminary Description © 2005 Microchip Technology Inc. ...
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... I REF Legend: CMOS = CMOS compatible input or output Analog Schmitt Trigger input with CMOS levelsO Input P © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Buffer Type ST Synchronous serial clock input/output for I ST Synchronous serial data input/output for I — 32 kHz low power oscillator crystal output. ...
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... NOTES: DS70139C-page 16 Preliminary © 2005 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes, and most instructions can address data either as words or bytes. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Two ways to access data in program memory are: • The upper 32 Kbytes of data space memory can ...
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... The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The program counter is 23-bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. Preliminary © 2005 Microchip Technology Inc. ...
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... DSP AccA Accumulators AccB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer SPLIM AD31 AD15 PC0 ...
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... DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function W0; Rem W1 W0; Rem W1 W0; Rem W1 W0; Rem W1 W0; Rem W1 Preliminary © 2005 Microchip Technology Inc. ...
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... ED EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70139C-page 22 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Preliminary Round u Logic Zero Backfill © 2005 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter, prior to accumulation. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true, or complement data into the other input ...
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... Section 2.4.2.4). Note that for the MAC class of instructions, the accumulator write back operation will function in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Preliminary © 2005 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... NOTES: DS70139C-page 26 Preliminary © 2005 Microchip Technology Inc. ...
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... The program space memory map for the dsPI30F2011/ 2012 is shown in Figure 3-1. The program space memory map for the dsPI30F3012/3013 is shown in Figure 3-2. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program memory is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1 ...
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... Program Memory (8K instructions) 003FFE 004000 Reserved (Read ‘0’s) 7FFBFE 7FFC00 Data EEPROM (1 Kbyte) 7FFFFE 800000 Reserved 8005BE 8005C0 UNITID (32 instr.) 8005FE 800600 Reserved F7FFFE Device Configuration F80000 Registers F8000E F80010 Reserved FEFFFE FF0000 DEVID (2) FFFFFE © 2005 Microchip Technology Inc. ...
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... Program 0 Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 ...
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... Byte: Read one of the MS Bytes of the program address; P<23:16> maps to the destination byte when byte select = 0; The destination byte will always when byte select = 1. 4. TBLWTH: Table Write High (refer to Section 5.0 for details on Flash Programming TBLRDL.B (Wn<0> TBLRDL.W TBLRDL.B (Wn<0> Preliminary 0 © 2005 Microchip Technology Inc. ...
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... Figure 3-6), only the lower 16 bits of the 24-bit program word are used to contain the data. The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the Programmer’s Reference Manual (DS70030) for details on instruction encoding. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn< ...
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... W0 ; Access program memory location ; using a data space access Note: PSVPAG is an 8-bit register, containing bits <22:15> of the program space address. DS70139C-page 32 Program Space 0x0000 (1) PSVPAG 0x00 8 0x8000 23 15 Address Concatenation 15 23 0xFFFF Preliminary 0x000000 0 0x001200 0x001FFF Data Read © 2005 Microchip Technology Inc. ...
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... W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map for the dsPIC30F2011 and dsPIC30F2012 is shown in Figure 3-7. The data space memory map for the dsPIC30F3012 and dsPIC30F3013 is shown in Figure 3-8. 16 bits ...
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... Optionally Mapped into Program Memory 0xFFFF DS70139C-page 34 LS Byte 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE 0x0800 X Data RAM (X) 0x0BFE 0x0C00 Y Data RAM (Y) 0x0FFE 0x1000 0x1FFE 0x8000 X Data Unimplemented (X) 0xFFFE Preliminary 8 Kbyte Near Data Space © 2005 Microchip Technology Inc. ...
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... FIGURE 3-9: DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 ...
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... FIGURE 3-10: MS Byte 15 0001 Byte1 0x0000 Byte3 0003 0x0000 Byte5 0005 0x0000 Preliminary backward compatibility with DATA ALIGNMENT LS Byte 0000 Byte 0 Byte 2 0002 Byte 4 0004 © 2005 Microchip Technology Inc. ...
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... PC<22:16> <Free Word> W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the stack pointer. SPLIM is uninitialized at Reset the case for the stack pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word aligned ...
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... DS70139C-page 38 Preliminary © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 39 ...
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... NOTES: DS70139C-page 40 Preliminary © 2005 Microchip Technology Inc. ...
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... Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... The only exception to the usage restrictions is for buff- ers which have a power-of-2 length. As these buffers satisfy the start and end address criteria, they may operate in a Bidirectional mode (i.e., address boundary checks will be performed on both the lower and upper address boundaries). Preliminary © 2005 Microchip Technology Inc. ...
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... Kbytes). Byte Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister MODCON<15:0> contains enable flags as well register field to specify the W address registers. ...
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... If bit-reversed addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to the XBREV register should not be immediately followed by bit-reversed an indirect read operation using the W register that has been designated as the bit-reversed pointer. Preliminary N bytes, addressing and bit-reversed © 2005 Microchip Technology Inc. ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value ...
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... NOTES: DS70139C-page 46 Preliminary © 2005 Microchip Technology Inc. ...
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... Using NVMADR Addressing Using Table Instruction User/Configuration Space Select © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... NVMKEY register. Refer to Section 5.6 for DD further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Preliminary © 2005 Microchip Technology Inc. ...
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... MOV #0xAA,W1 MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... Write PM high byte into program latch ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Preliminary © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 51 ...
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... NOTES: DS70139C-page 52 Preliminary © 2005 Microchip Technology Inc. ...
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... EEPROM write/erase operation. Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software ...
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... Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence ; Block all interrupts with priority <7 for ; next 5 instructions ; ; Write the 0x55 key ; ; Write the 0xAA key ; Initiate erase sequence Preliminary © 2005 Microchip Technology Inc. ...
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... NOP ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The write will not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EEPROM writes, various mechanisms have been built-in. On power-up, the WREN bit is cleared; also, the Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together help prevent an accidental write during brown-out, power glitch, or software malfunction. Preliminary © 2005 Microchip Technology Inc. ...
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... WR TRIS WR LAT + WR Port Read LAT Read Port © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Any bit and its associated data and control registers that are not valid for a particular device will be dis- abled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. ...
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... Typically this instruction would be a NOP will be OL EXAMPLE 7-1: MOV #0xF0, W0; Configure PORTB<7:4> MOV W0, TRISB; and PORTB<3:0> as outputs NOP btss PORTB, #7; bit test RB7 and skip if set Preliminary PORT WRITE/READ EXAMPLE ; as inputs ; additional instruction cycle © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 59 ...
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... DS70139C-page 60 Preliminary © 2005 Microchip Technology Inc. ...
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... CN7IE CN6IE CNEN2 00C2 — — CNPU1 00C4 CN7PUE CN6PUE CNPU2 00C6 — — TABLE 7-8: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2012/3013 (BITS 7-0) SFR Addr. Bit 7 Bit 6 Name CNEN1 00C0 CN7IE CN6IE CNEN2 00C2 — — CNPU1 00C4 ...
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... NOTES: DS70139C-page 62 Preliminary © 2005 Microchip Technology Inc. ...
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... The current CPU priority level is explicitly stored in the IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers ...
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... LVD - Low Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority * Only the dsPIC30F3013 has UART2 and the U2RX, U2TX interrupts. These locations are reserved for the dsPIC30F2011/2012/3012. Preliminary © 2005 Microchip Technology Inc. Interrupt Source 2 C Slave Interrupt 2 C Master Interrupt ...
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... A momentary dip in the power supply to the device has been detected which may result in malfunction. • Trap Lockout: Occurrence of multiple trap conditions simultaneously will cause a Reset. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 8.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 8-1 ...
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... The device is automatically Reset in a hard trap conflict condition. The TRAPR status bit (RCON<15>) is set when the Reset occurs, so that the condition may be detected in software. Preliminary © 2005 Microchip Technology Inc. ...
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... The processor then loads the priority level for this inter- rupt into the STATUS register. This action will disable all lower priority interrupts until the completion of the Interrupt Service Routine. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 8-2: 0x000000 0x000002 ...
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... At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. Preliminary © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 69 ...
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... DS70139C-page 70 Preliminary © 2005 Microchip Technology Inc. ...
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... TGATE SOSCO/ T1CK LPOSCEN SOSCI © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These Operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Low power • Real-Time Clock interrupts These operating modes are determined by setting the appropriate bit(s) in the T1CON Control register. FIGURE 9-2: RECOMMENDED COMPONENTS FOR TIMER1 LP OSCILLATOR RTC C1 32.768 kHz XTAL pF 100K Preliminary SOSCI dsPIC30FXXXX SOSCO © 2005 Microchip Technology Inc. ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt will be generated if enabled ...
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... DS70139C-page 74 Preliminary © 2005 Microchip Technology Inc. ...
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... Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 interrupt enable bit (T3IE). © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16-bit Timer Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers ...
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... Timer configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70139C-page TMR3 TMR2 MSB LSB Comparator x 32 PR3 PR2 TGATE (T2CON<6> Gate Sync ’ for a 32-bit timer/counter operation. All control Preliminary Sync TCKPS<1:0> TON 2 Prescaler 1, 8, 64, 256 © 2005 Microchip Technology Inc. ...
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... TIMER2 BLOCK DIAGRAM Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 PR2 Comparator x 16 TMR2 TGATE Gate Sync PR3 Comparator x 16 TMR3 ...
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... In this mode, the T3IF interrupt flag is used as the source of the interrupt. The T3IF bit must be cleared in software. Enabling an interrupt is accomplished via the respective timer interrupt enable bit, T3IE (IEC0<7>). Preliminary © 2005 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 79 ...
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... NOTES: DS70139C-page 80 Preliminary © 2005 Microchip Technology Inc. ...
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... Data Bus Note: Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input capture channel (1 or 2). © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bits in the IC1CON and IC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have two capture channels ...
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... IFSx Status register. Enabling an interrupt is accomplished via the respec- tive capture channel interrupt enable (ICxIE) bit. The capture interrupt enable bit is located in the corresponding IEC Control register. Preliminary © 2005 Microchip Technology Inc. module is defined as ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 83 ...
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... NOTES: DS70139C-page 84 Preliminary © 2005 Microchip Technology Inc. ...
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... TMR2<15:0 TMR3<15:0> Note: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channel (1 or 2). © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The key operational features of the output compare module include: • Timer2 and Timer3 Selection mode • Simple Output Compare Match mode • ...
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... FAULT condition has occurred. This state will be maintained until both of the following events have occurred: • The external FAULT condition has been removed. • The PWM mode has been re-enabled by writing to the appropriate control bits. Preliminary . © 2005 Microchip Technology Inc. ...
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... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
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... DS70139C-page 88 Preliminary © 2005 Microchip Technology Inc. ...
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... SDO1 SS & FSYNC Control SS1 SCK1 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • SS1 (active low slave select). In Master mode operation, SCK1 is a clock output. In Slave mode clock input. A series of eight (8) or sixteen (16) clock pulses shift out bits from the SPI1SR to SDO1 pin and simulta- neously shift in data from SDI1 pin ...
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... SPI clock cycle. When frame synchronization is enabled, the data transmission starts only on the subsequent transmit edge of the SPI clock. SDO1 SDI1 Serial Input Buffer SDI1 SDO1 MSb Serial Clock SCK1 SCK1 Preliminary SPI™ Slave (SPI1BUF) Shift Register (SPI1SR) LSb PROCESSOR 2 © 2005 Microchip Technology Inc. ...
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... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 13.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPI1STAT< ...
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... DS70139C-page 92 Preliminary © 2005 Microchip Technology Inc. ...
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... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
Page 96
... Addr_Match Match Detect I2CADD Start and Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control I2CBRG BRG Down Counter F CY Preliminary Internal Data Bus Read Write Read Write Read Write Read Write Read Write Read © 2005 Microchip Technology Inc. ...
Page 97
... SCL, such that SDA is valid during SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘ ...
Page 98
... SCLREL bit will not violate the minimum high time requirement for SCL. If the STREN bit is ‘0’, a software write to the SCLREL bit will be disregarded and have no effect on the SCLREL bit. Preliminary © 2005 Microchip Technology Inc. 2 CRCV ...
Page 99
... When the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific or a general call address. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 14. Master Support As a master device, six operations are supported: ...
Page 100
... For the I C, the I2CSIDL bit selects if the module will stop on Idle or continue on Idle. If I2CSIDL = 0, the module will continue operation on assertion of the Idle mode. If I2CSIDL = 1, the module will stop on Idle. Preliminary 2 C master event Interrupt Service Rou © 2005 Microchip Technology Inc ...
Page 101
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 99 ...
Page 102
... NOTES: DS70139C-page 100 Preliminary © 2005 Microchip Technology Inc. ...
Page 103
... Internal Data Bus UTXBRK Data UxTX Parity Note © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.1 UART Module Overview The key features of the UART module are: • Full-duplex 9-bit data communication • Even, odd or no parity options (for 8-bit data) • One or two Stop bits • ...
Page 104
... Receive Buffer Control 8-9 Load RSR to Buffer Receive Shift Register (UxRSR) 16 Divider 16x Baud Clock from Baud Rate Generator Preliminary Read Read Write UxMODE UxSTA – Generate Flags – Generate Interrupt – Shift Data Characters Control Signals UxRXIF © 2005 Microchip Technology Inc. ...
Page 105
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.3 Transmitting Data 15.3.1 ...
Page 106
... UxRSR needs to transfer the character to the buffer. Once OERR is set, no further data is shifted in UxRSR (until the OERR bit is cleared in software or a Reset occurs). The data held in UxRSR and UxRXREG remains valid. Preliminary © 2005 Microchip Technology Inc. RXB) X ...
Page 107
... FERR bit set. The break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.6 Address Detect Mode Setting the ADDEN bit (UxSTA< ...
Page 108
... For the UART, the USIDL bit selects if the module will stop operation when the device enters Idle mode or whether the module will continue on Idle. If USIDL = 0, the module will continue operation during Idle mode. If USIDL = 1, the module will stop on Idle. Preliminary © 2005 Microchip Technology Inc. ...
Page 109
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139C-page 107 ...
Page 110
... NOTES: DS70139C-page 108 Preliminary © 2005 Microchip Technology Inc. ...
Page 111
... AN6 0111 AN7 1000 AN8 1001 AN9 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The A/D module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • ...
Page 112
... The inputs are always scanned from lower to higher numbered inputs, starting after each interrupt. If the number of inputs selected is greater than the number of samples taken per interrupt, the higher numbered inputs are unused. Preliminary © 2005 Microchip Technology Inc. ...
Page 113
... 667 nsec (for V = 5V). Refer to the Electrical DD Specifications section for minimum T operating conditions. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example 16-1 shows a sample calculation for the ADCS<5:0> bits, assuming a device operating speed of 30 MIPS. EXAMPLE 16-1: Minimum T ADCS< ...
Page 114
... The A/D result is 12 bits wide. The data buffer RAM is also 12 bits wide. The 12-bit data can be read in one of four different formats. The FORM<1:0> bits select the format. Each of the output formats translates to a 16-bit result on the data bus. Preliminary HOLD = DAC capacitance = negligible © 2005 Microchip Technology Inc. ...
Page 115
... Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 0 ...
Page 116
... DS70139C-page 114 Preliminary © 2005 Microchip Technology Inc. ...
Page 117
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Preliminary DS70139C-page 115 ...
Page 118
... NOTES: DS70139C-page 116 Preliminary © 2005 Microchip Technology Inc. ...
Page 119
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 120
... RC oscillator. Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation MHz. DS70139C-page 118 Description (1) . (2) . (1) . (1) . (3) /4 output . OSC (3) . Preliminary © 2005 Microchip Technology Inc. (1) . ...
Page 121
... FIGURE 17-1: OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Internal FRC Osc Primary Oscillator Stability Detector ...
Page 122
... OSC2 Function OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 1 1 OSC2 0 1 OSC2 1 0 OSC2 OSC2 0 0 OSC2 1 0 CLKOUT 1 1 CLKOUT OSC2 0 0 (Note (Note (Note © 2005 Microchip Technology Inc. ...
Page 123
... Table 17-4. If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00001’, ‘01010’ or ‘00011’, then a PLL multiplier (respectively) is applied. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7 ...
Page 124
... Byte Write “0x78” to OSCCON high Byte Write “0x9A” to OSCCON high Byte write is allowed for one instruction cycle . Write the desired value or use bit manipulation instruction. Preliminary © 2005 Microchip Technology Inc. ...
Page 125
... Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected ...
Page 126
... INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset DS70139C-page 124 T OST T PWRT T OST T PWRT T OST T PWRT Preliminary ) DD ): CASE CASE 2 DD © 2005 Microchip Technology Inc. ...
Page 127
... Refer to the Electrical Specifications in the specific device data sheet for BOR voltage limit specifications. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 A BOR will generate a Reset pulse which will reset the device. The BOR will select the clock source based on the device configuration bit values (FOS< ...
Page 128
... When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. DS70139C-page 126 TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( TRAPR IOPUWR EXTR SWR WDTO IDLE SLEEP POR BOR ( Preliminary © 2005 Microchip Technology Inc. ...
Page 129
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.6 Power Saving Modes There are two power saving states that can be entered through the execution of a special instruction, PWRSAV ...
Page 130
... For addi- tional information, please refer to the Programming Specifications of the device. Note: If the code protection configuration fuse bits (FGS<GCP> and FGS<GWRP>) have been programmed, an erase of the entire code-protected device is only possible at voltages V Preliminary © 2005 Microchip Technology Inc. 4.5V. DD ...
Page 131
... Note: In the dsPIC30F2011, dsPIC30F3012 and dsPIC30F2012 devices, the U2MD bit is readable and writable and will be read as ‘1’ when set. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17 ...
Page 132
... DS70139C-page 130 Preliminary © 2005 Microchip Technology Inc. ...
Page 133
... The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • ...
Page 134
... Programmer’s Reference Manual. Description {W13, [W13]+=2} {0...15} {0x0000...0x1FFF} {0,1} {0...15} {0...31} {0...255} {0...255} for Byte mode, {0:1023} for Word mode {0...16384} {0...65535} {0...8388608}; LSB must be 0 {-512...511} {-32768...32767} {-16...16} Preliminary © 2005 Microchip Technology Inc. ...
Page 135
... Y data space pre-fetch address register for DSP instructions {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Wyd Y data space pre-fetch destination register for DSP instructions © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0 ...
Page 136
... Branch if Accumulator B overflow Branch if Overflow Branch if Accumulator A saturated Branch if Accumulator B saturated Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws<Wb> Write Z bit to Ws<Wb> Preliminary © 2005 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 OA,OB,SA, C,DC,N,OV,Z ...
Page 137
... DEC Ws,Wd 28 DEC2 DEC2 f DEC2 f,WREG DEC2 Ws,Wd © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 138
... Move 16-bit literal to Wn Move 8-bit literal to Wn Move Move Move WREG to f Move Double from W(ns):W(ns+ Move Double from Ws to W(nd+1):W(nd) Pre-fetch and store accumulator Preliminary © 2005 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 None ...
Page 139
... RRC Ws,Wd 67 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) ...
Page 140
... Read Prog<23:16> to Wd<7:0> Read Prog<15:0> Write Ws<7:0> to Prog<23:16> Write Ws to Prog<15:0> Unlink frame pointer .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR .XOR .XOR. lit5 Wnd = Zero-extend Ws Preliminary © 2005 Microchip Technology Inc Status Flags Words Cycles Affected 1 1 None 1 1 None ...
Page 141
... OQ - PICDEM MSC ® - microID - CAN ® - PowerSmart - Analog © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. The MPLAB IDE is a Windows based application that contains: • ...
Page 142
... MPLAB C30 C Compiler and MPLAB ASM30 assembler. The simulator runs in either a Command Line mode for automated tasks, or from MPLAB IDE. This high-speed simulator is designed to debug, analyze and optimize time intensive DSP routines. Preliminary © 2005 Microchip Technology Inc. economical software ...
Page 143
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.11 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, ...
Page 144
... PICSTART Plus development pro- grammer, can be used to reprogram the device for user tailored application development. The PICDEM 17 demonstration board supports program download and execution from external on-board Flash memory. A generous prototype area is available for user hardware expansion. Preliminary © 2005 Microchip Technology Inc. ...
Page 145
... PIC Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM USB Demonstration Board shows off the capabilities of the PIC16C745 and PIC16C765 USB microcontrollers ...
Page 146
... NOTES: DS70139C-page 144 Preliminary © 2005 Microchip Technology Inc. ...
Page 147
... DD 4.5-5.5V -40°C to 85°C 4.5-5.5V -40°C to 125°C 3.0-3.6V -40°C to 85°C 3.0-3.6V -40°C to 125°C 2.5-3.0V -40°C to 85°C © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (except V and MCLR) (Note 1) .................................... -0. ..........................................................................................................± > ................................................................................................... ± pin, inducing currents greater than 80 mA, may cause latchup. ...
Page 148
... Max Unit Notes 44 — °C — °C — °C — °C — °C/W 1 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Units Conditions V Industrial temperature V Extended temperature V V V/ms 0-5V in 0.1 sec 0- © 2005 Microchip Technology Inc. ...
Page 149
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 150
... OSC1 DD Preliminary +85°C for Industrial +125°C for Extended 20 MIPS EC mode, 8X PLL 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS) LPRC (~ 512 kHz © 2005 Microchip Technology Inc. ...
Page 151
... Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Base I current is measured with Core off, Clock on and all modules turned off. IDLE © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 ) IDLE Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
Page 152
... Preliminary +85°C for Industrial +125°C for Extended 20 MIPS EC mode, 8X PLL 16 MIPS EC mode, 16X PLL 30 MIPS EC mode, 16X PLL FRC (~ 2 MIPS) LPRC (~ 512 kHz) © 2005 Microchip Technology Inc. ...
Page 153
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C ...
Page 154
... Operating temperature -40° -40° Units Conditions A -40°C A 25°C 3.3V A 85°C A 125°C A -40°C A 25° 85°C A 125°C Preliminary ) (CONTINUED) PD +85°C for Industrial +125°C for Extended (3) Low Voltage Detect: I LVD © 2005 Microchip Technology Inc. ...
Page 155
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 5: Negative current is defined as current sourced by the pin. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 156
... Preliminary T +85°C for Industrial A +125°C for Extended A Units Conditions 8.5 mA 2.0 mA 1.6 mA 2.0 mA -3.0 mA -2.0 mA -1.3 mA -2.0 mA XTL, XT, HS and LP modes when external clock is used to drive OSC1 Osc mode mode © 2005 Microchip Technology Inc. ...
Page 157
... These parameters are characterized but not tested in manufacturing. 2: These values not in usable operating range. FIGURE 20-2: BROWN-OUT RESET CHARACTERISTICS V DD BO10 (Device in Brown-out Reset) RESET (due to BOR) © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) Min (2) transition LVDL = 0000 — ...
Page 158
... V 4.46 V 4.78 V — +85°C for Industrial A T +125°C for Extended A Conditions - +85° Using EECON to read/write V = Minimum operating MIN voltage ms are violated Row Erase - +85° Minimum operating MIN voltage are violated ms Row Erase Bulk Erase © 2005 Microchip Technology Inc. ...
Page 159
... FIGURE 20-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSC2 Pin FIGURE 20-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T Operating voltage V range as described in DC Spec Section 20 ...
Page 160
... MHz HS/3 with 16x PLL kHz LP MHz FRC internal MHz FRC internal w/4x PLL MHz FRC internal w/8x PLL MHz FRC internal w/16x PLL kHz LPRC internal — See parameter OS10 for F value OSC ns See Table 20- © 2005 Microchip Technology Inc. ...
Page 161
... Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle]. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T (1) (2) Min Typ Max (2) 4 — ...
Page 162
... V = 3.0-3.6V DD +25° 4.5-5. +85° 3.0-3. +85° 4.5-5. +125° 4.5-5. +25° 3.0-3.6V DD +25° 4.5-5. +85° 3.0-3. +85° 4.5-5. +125° 4.5-5. +25° 3.0-3.6V DD +25° 4.5-5. +85° 3.0-3. +85° 4.5-5. +125° 4.5-5. © 2005 Microchip Technology Inc. ...
Page 163
... Frequency calibrated at 25°C and 5V. TUN bits can be used to compensate for temperature drift. TABLE 20-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. LPRC @ Freq = 512 kHz F20 F21 Note 1: Frequency at 25°C and 5V. 2: Change of LPRC frequency as V © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 -40°C T -40°C T Min Typ Max Units (1) TBD % ...
Page 164
... Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1)(2)(3) (4) Min Typ Max — — — — — — CY Preliminary +85°C for Industrial +125°C for Extended Units Conditions ns — ns — ns — ns — . OSC © 2005 Microchip Technology Inc. ...
Page 165
... V DD SY12 MCLR Internal POR SY11 PWRT Time-out SY30 OSC Time-out Internal RESET Watchdog Timer RESET I/O Pins SY35 FSCM Delay Note: Refer to Figure 20-3 for load conditions. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SY10 SY13 Preliminary SY20 SY13 DS70139C-page 163 ...
Page 166
... User programmable s -40°C to +85° 5V, -40°C to +85° 3V, -40°C to +85° (D034) DD BOR — OSC1 period OSC s -40°C to +85°C V BGAP Band Gap Stable © 2005 Microchip Technology Inc. ...
Page 167
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. FIGURE 20-8: TYPE A, B AND C TIMER EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK TMRX Note: Refer to Figure 20-3 for load conditions. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40° ...
Page 168
... Industrial A +125°C for Extended A Max Units Conditions — ns Must also meet parameter TA15 — ns — ns — ns Must also meet parameter TA15 — ns — ns — ns — — prescale value (1, 8, 64, 256) — kHz 6 T — OSC © 2005 Microchip Technology Inc. ...
Page 169
... TtxP TxCK Input Period Synchronous, TC20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer3 and Timer5 are Type C. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature Min Typ Synchronous, 0 — ...
Page 170
... Typ Max — — Preliminary +85°C for Industrial +125°C for Extended Max Units Conditions — ns — ns — ns — ns — prescale value (1, 4, 16) +85°C for Industrial A T +125°C for Extended A Units Conditions ns — ns — © 2005 Microchip Technology Inc. ...
Page 171
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 172
... CS56 CS35 CS51 CS50 HIGH-Z CSDO CSDI Note: Refer to Figure 20-3 for load conditions. DS70139C-page 170 2 S MODES) TIMING CHARACTERISTICS CS11 CS10 CS21 CS20 MSb CS30 MSb IN CS40 CS41 Preliminary CS20 CS21 70 LSb HIGH-Z CS31 LSb IN © 2005 Microchip Technology Inc. ...
Page 173
... The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all DCI pins. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 S MODES) TIMING REQUIREMENTS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 174
... Preliminary CS20 CS70 CS75 LSb CS75 +85°C for Industrial A T +125°C for Extended A Units Conditions ns — ns — ns Bit clock is input ns — ns — s Note 1 s Note 1 s Note pF LOAD pF LOAD pF LOAD pF LOAD DD ns — © 2005 Microchip Technology Inc. ...
Page 175
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP10 SP21 SP20 BIT14 - - - - - -1 MSb ...
Page 176
... X data input 20 — X Preliminary SP20 SP21 -40°C T +85°C for Industrial A -40°C T +125°C for Extended A Max Units Conditions — ns — — ns — — — — — — — ns — — ns — — ns — © 2005 Microchip Technology Inc. ...
Page 177
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP70 SP73 SP72 MSb ...
Page 178
... SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 20-3 for load conditions. DS70139C-page 176 SP70 SP73 SP35 SP72 SP52 BIT14 - - - - - -1 LSb SP30,SP31 BIT14 - - - -1 LSb IN Preliminary SP52 SP72 SP73 SP51 © 2005 Microchip Technology Inc. ...
Page 179
... The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 180
... C BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 20-3 for load conditions. DS70139C-page 178 IM11 IM10 IM26 IM25 IM40 Preliminary IM34 IM33 Stop Condition IM21 IM33 IM45 © 2005 Microchip Technology Inc. ...
Page 181
... Note 1: BRG is the value of the I C Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit™ the dsPIC30F Family Reference Manual. 2: Maximum pin capacitance = 10 pF for all I © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 182
... IS31 IS30 SDA Start Condition 2 FIGURE 20-21 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 SCL IS30 IS31 SDA In IS40 SDA Out DS70139C-page 180 IS33 IS11 IS10 IS26 IS25 IS40 Preliminary IS34 Stop Condition IS21 IS33 IS45 © 2005 Microchip Technology Inc. ...
Page 183
... Clock IS45 T : Bus Free Time BF SDA IS50 C Bus Capacitive B Loading Note 1: Maximum pin capacitance = 10 pF for all I © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° Min Max 100 kHz mode 4.7 — ...
Page 184
... CA10 CA11 CA20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° (1) (2) Min Typ Max — — 500 Preliminary New Value +85°C for Industrial +125°C for Extended Units Conditions ns — ns — ns — © 2005 Microchip Technology Inc. ...
Page 185
... Gain Error ERR AD23A G Gain Error ERR Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C Min. ...
Page 186
... TBD — — — 50 kHz — TBD TBD Preliminary +85°C for Industrial +125°C for Extended Conditions INL SS REFL 0V REFH INL SS REFL 0V REFH — Guaranteed dB — dB — dB — dB — dB — dB — — bits — © 2005 Microchip Technology Inc. ...
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... Family Reference Manual , Section 18. T SAMP 3 - Software clears ADCON. SAMP to start conversion Sampling ends, conversion sequence starts Convert bit 11 Convert bit 10 Convert bit Convert bit One T for end of conversion. AD © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 AD55 Confidential DS70139C-page 185 ...
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... AD Timing Parameters — — 0.5 T — 1 — — TBD ns — — TBD Preliminary +85°C for Industrial A T +125°C for Extended A Conditions V = 3-5.5V (Note — — REF V = 3-5.5V source DD resistance R = 0-2 — — — s — © 2005 Microchip Technology Inc. ...
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... For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example dsPIC30F3012 30I/P Example dsPIC30F2011 e 30I/SO 0510017 Example dsPIC30F2012 30I/SP Preliminary e 3 0510017 0510017 ...
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... Package Marking Information (Continued) 28-Lead SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXX XXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS70139C-page 188 Example dsPIC30F3013 e 30I/SO 0510017 Example 30F2011 e 30I/MM 3 0510017 Example dsPIC 30F3013 e 30I/ML 3 0510017 Preliminary © 2005 Microchip Technology Inc. 3 ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Units INCHES* ...
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... Preliminary A2 MILLIMETERS MIN NOM MAX 18 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.39 7.49 7.59 11.33 11.53 11.73 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.27 0.30 0.36 0.42 0. © 2005 Microchip Technology Inc. ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Units INCHES* MIN ...
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... Preliminary a A2 MILLIMETERS MIN NOM MAX 28 1.27 2.36 2.50 2.64 2.24 2.31 2.39 0.10 0.20 0.30 10.01 10.34 10.67 7.32 7.49 7.59 17.65 17.87 18.08 0.25 0.50 0.74 0.41 0.84 1. 0.23 0.28 0.33 0.36 0.42 0. © 2005 Microchip Technology Inc. ...
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... Number of Pins Pitch Overall Height Standoff Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length *Controlling Parameter Notes: JEDEC equivalent: MO-220 Drawing No. C04-124 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 EXPOSED METAL PAD OPTIONAL ALTERNATE INDEX INDEX ...
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... Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) DS70139C-page 194 Preliminary © 2005 Microchip Technology Inc. ...
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... Sequence Table (16-Entry)......................................... 45 Block Diagrams 12-bit A/D Functional ................................................ 109 16-bit Timer1 Module .................................................. 71 16-bit Timer2............................................................... 77 16-bit Timer3............................................................... 77 32-bit Timer2/3............................................................ 76 DSP Engine ................................................................ 22 dsPIC30F2011 ............................................................ 10 dsPIC30F2012 ............................................................ 11 dsPIC30F3013 ............................................................ 13 External Power-on Reset Circuit............................... 125 2 I C............................................................................... 94 Input Capture Mode .................................................... 81 © 2005 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Oscillator System...................................................... 119 Output Compare Mode ...
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... Programmer’s Model .................................................. 93 Register Map .............................................................. 99 Registers .................................................................... 93 Slope Control .............................................................. 97 Software Controlled Clock Stretching (STREN = 1) ... 96 Various Modes............................................................ 93 Idle Current (I ) ............................................................ 149 IDLE In-Circuit Serial Programming (ICSP)......................... 47, 117 Input Capture (CAPX) Timing Characteristics .................. 168 Input Capture Module ......................................................... 81 Interrupts .................................................................... 82 Register Map .............................................................. 83 Preliminary © 2005 Microchip Technology Inc. ...
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... Input Capture Operation During Sleep and Idle Modes ...... 82 CPU Idle Mode............................................................ 82 CPU Sleep Mode ........................................................ 82 Input Capture Timing Requirements ................................. 168 Input Change Notification Module ....................................... 61 dsPIC30F2012/3013 Register Map (Bits 7-0) ............. 61 Instruction Addressing Modes............................................. 41 File Register Instructions ............................................ 41 Fundamental Modes Supported.................................. 41 MAC Instructions......................................................... 42 MCU Instructions ........................................................ 41 Move and Accumulator Instructions ...
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... Input Capture (CAPX)............................................... 168 OC/PWM Module...................................................... 169 Oscillator Start-up Timer........................................... 163 Output Compare Module .......................................... 168 Power-up Timer ........................................................ 163 Reset ........................................................................ 163 SPI Module Master Mode (CKE = 0).................................... 173 Master Mode (CKE = 1).................................... 174 Slave Mode (CKE = 0)...................................... 175 Slave Mode (CKE = 1)...................................... 176 Preliminary © 2005 Microchip Technology Inc. ...